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IEEE SQRT 32-bit Floating-point Square-root IP Core Rev. 1.2 Key Design Features Block Diagram Synthesizable, technology independent IP Core for FPGA, ASIC and SoC Supplied as human readable VHDL (or Verilog) source code 32-bit floating-point arithmetic v1 vout 1 IEEE 754 compliant High-speed fully pipelined architecture Variable latency from 2 to 24 clock cycles VOUT = V1 en Applications clk Floating-point pipelines and arithmetic units Floating-point processors Figure 1: 32-bit Floating-point Square-root Pin-out Description General Description Pin name I/O Description Active state The IEEE SQRT IP Core (Figure 1) is a high-speed fully pipelined 32-bit bit floating-point square-root function based on the IEEE 754 standard. clk in Synchronous clock rising edge The arrangement of the 32-bit floating-point number is summarized en in Clock enable high below: v1 31:0 in Input operand in IEEE 754 data format MSB LSB vout 31:0 out Output result in IEEE 754 data Sign Exponent Mantissa format (1-bit) (8-bits) (23-bits) reg stages in Generic parameter fixes N/A latency at compile time All input and output values comply with the IEEE 754 specification. The real number representation is calculated according to the formula: Functional Specification (E127) Operand v1 Result Value=1(S)2 1.M Standard IEEE v1 The square-root is fully compliant with the IEEE 754 specification with the If v1 > MaxFloat then result is Inf exception that denormalized (subnormal) numbers are treated as zero throughout the implementation. In addition, all input operands are If v1 MinFloat then result is 0 assumed to be unsigned. The maximum floating-point value that may be represented in hex is 0x7F7FFFFF or 0xFF7FFFFF (+/- MaxFloat). (Inputs are assumed unsigned) Likewise, the minimum floating-point value that may be represented is 0x00800000 or 0x80800000 (+/- MinFloat). This means that a real number lies in the range: NaN NaN Inf Inf 126 127 23 0 0 2 Value 2 22 Other points to note are that a NaN is always generated as the value 0xFFC00000. By default, the square-root result uses round towards zero, although other rounding methods are available on request. All values are sampled on the rising clock-edge of clk when en is high. The latency of the square-root pipeline is generic and may be fixed during synthesis. Integer values of between 2 and 24 clock cycles are possible, 1 Some minor features diverge from the IEEE 754 specification Copyright 2018 www.zipcores.com Download this IP Core Page 1 of 2IEEE SQRT 32-bit Floating-point Square-root IP Core Rev. 1.2 The overall latency given by a round-up of the following calculation: Synthesis and Implementation Latency =(23 / reg stages)+ 1 The source files required for synthesis and the design hierarchy is shown below: Functional Timing ieee sqrt.vhd ieee sqrt pipe.vhd ieee sqrt subsquare.vhd Figure 2 demonstrates the square-root of 0x3FA00000 (or 1.25 = 1.118034 in real numbers). In this particular case, the generic parameter reg stages has been set to 12 giving a result with a latency of 3 clock The VHDL core is designed to be technology independent. However, as a cycles (23/12+1). benchmark, synthesis results have been provided for the Xilinx 7-series FPGAs. Synthesis results for other FPGAs and technologies can be provided on request. clk By adding more pipeline stages (reducing the value of the reg stage generic) will result in faster implementations. Conversely, reducing the en number of pipeline stages will generally result in a smaller but slower design. v1 0x3FA00000 Trial synthesis results are shown with a setting of reg stages = 1 (maximum pipelining). Resource usage is specified after Place and Route. vout 0x3F8F1BBD XILINX 7-SERIES FPGAS Resource type Artix-7 Kintex-7 Virtex-7 Figure 2: Square-root of a floating-point number with the pipeline latency fixed at 3 clock cycles Slice Register 861 861 861 Slice LUTs 1148 1146 1147 Source File Description Block RAM 0 0 0 DSP48 44 44 44 All source files are provided as text files coded in VHDL. The following Occupied Slices 460 435 440 table gives a brief description of each file. Clock freq. (approx) 150 MHz 200 MHz 250 MHz Source file Description Revision History ieee sqrt subquare.vhd Pipelined sqaure-root subtract- square module ieee sqrt pipe.vhd Pipelined square-root module Revision Change description Date ieee sqrt.vhd Top-level component 1.0 Initial revision 18/10/2010 ieee sqrt bench.vhd Top-level test bench 1.1 Added reg stages generic to allow flexible 25/11/2011 pipeline depths. Updated synthesis results. Functional Testing 1.2 Cosmetic changes to the source code 02/07/2018 An example VHDL testbench is provided for use in a suitable VHDL Updated results for Xilinx 7-series simulator. The compilation order of the source code is as follows: 1. ieee sqrt subsquare.vhd 2. ieee sqrt pipe.vhd 3. ieee sqrt.vhd 4. ieee sqrt bench.vhd The simulation must be run for at least 2 ms during which time an input stimulus of randomized floating-point numbers will generated at the module input. The simulation generates two text files called: ieee sqrt in.txt and ieee sqrt out.txt. These files respectively capture the input and output floating-point numbers during the course of the test. Copyright 2018 www.zipcores.com Download this IP Core Page 2 of 2