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IEEE DIV 32-bit Floating-point Divider IP Core Rev. 1.2 Key Design Features Block Diagram Synthesizable, technology independent IP Core for FPGA, ASIC and SoC v1 Supplied as human readable VHDL (or Verilog) source code 32-bit floating-point arithmetic vout 1 IEEE 754 compliant High-speed fully pipelined architecture v2 Variable latency from 2 to 49 clock cycles VOUT = V1 / V2 en Applications clk Floating-point pipelines and arithmetic units Floating-point processors Figure 1: 32-bit Floating-point Divider Pin-out Description General Description Pin name I/O Description Active state The IEEE DIV IP Core (Figure 1) is a high-speed fully pipelined 32-bit bit floating-point divider based on the IEEE 754 standard. The arrangement clk in Synchronous clock rising edge of the 32-bit floating-point number is summarized below: en in Clock enable high v1 31:0 in Input operand 1 in IEEE data 754 format MSB LSB Sign Exponent Mantissa v2 31:0 in Input operand 2 in IEEE data (1-bit) (8-bits) (23-bits) 754 format vout 31:0 out Output result in IEEE 754 data format All input and output values comply with the IEEE 754 specification. The reg stages in Generic parameter fixes N/A real number representation is calculated according to the formula: latency at compile time (E127) Value=1(S)2 1.M Functional Specification The divider is fully compliant with the IEEE 754 standard with the Operand v1 Operand v2 Result exception that denormalized (subnormal) numbers are treated as zero Standard IEEE Standard IEEE v1 / v2 throughout the implementation. The maximum floating-point value that may be represented in hex is 0x7F7FFFFF or 0xFF7FFFFF (+/- If v1 / v2 > MaxFloat then result is: MaxFloat). Likewise, the minimum floating-point value that may be sign(v1) xor sign(v2) Inf represented is 0x00800000 or 0x80800000 (+/- MinFloat). This means If v1 / v2 MinFloat then result is: that a real number lies in the range: sign(v1) xor sign(v2) 0 NaN Anything NaN 126 127 23 2 Value 2 22 Anything NaN NaN +/- Inf +/- Inf NaN Other points to note are that a NaN is always generated as the value +/- 0 +/- 0 NaN 0xFFC00000. By default, the divider uses round towards zero, although other rounding methods are available on request. +/- Inf Standard IEEE sign(v1) xor sign (v2) Inf Standard IEEE +/- Inf sign(v1) xor sign (v2) 0 All values are sampled on the rising clock-edge of clk when en is high. The latency of the divider pipeline is generic and may be fixed during +/- 0 Standard IEEE sign(v1) xor sign (v2) 0 synthesis. Standard IEEE +/- 0 sign(v1) xor sign (v2) Inf 1 Some minor features diverge from the IEEE 754 specification Copyright 2018 www.zipcores.com Download this IP Core Page 1 of 2IEEE DIV 32-bit Floating-point Divider IP Core Rev. 1.2 Integer values of between 2 and 49 clock cycles are possible, with the Synthesis and Implementation overall latency given by: The source files required for synthesis and the design hierarchy is shown Latency =(48 / reg stages)+ 1 below: Functional Timing ieee div.vhd ieee div pipe.vhd ieee div shiftsub.vhd Figure 2 demonstrates the division: 0x3FA00000 / 0x40333333 (or 1.25 / 2.8 = 0.44643 in real numbers). In this particular case, the generic parameter reg stages has been set to 24 giving a result with a latency of The VHDL core is designed to be technology independent. However, as a 3 clock cycles (48/24+1). benchmark, synthesis results have been provided for the Xilinx 7-series FPGAs. Synthesis results for other FPGAs and technologies can be provided on request. clk By adding more pipeline stages (reducing the value of the reg stage generic) will result in faster implementations. Conversely, reducing the en number of pipeline stages will generally result in a smaller but slower design. Generally, using around 13-17 pipeline stages will give the v1 0x3FA00000 optimal results. v2 0x40333333 Trial synthesis results are shown with a setting of reg stages = 1 (maximum pipelining). Resource usage is specified after Place and Route. vout 0x3EE49249 XILINX 7-SERIES FPGAS Figure 2: Division of two floating-point numbers with the Resource type Artix-7 Kintex-7 Virtex-7 pipeline latency fixed at 3 clock cycles Slice Register 2352 2352 2351 Slice LUTs 1489 1489 1442 Source File Description Block RAM 0 0 0 DSP48 0 0 0 All source files are provided as text files coded in VHDL. The following table gives a brief description of each file. Occupied Slices 451 451 449 Clock freq. (approx) 250 MHz 300 MHz 350 MHz Source file Description ieee div shiftsub.vhd Pipelined divider shift-subtract module Revision History ieee div pipe.vhd Pipelined divider module ieee div.vhd Top-level component Revision Change description Date ieee div bench.vhd Top-level test bench 1.0 Initial revision 30/04/2008 Functional Testing 1.1 Added reg stages generic to allow flexible 16/09/2011 pipeline depths. Updated synthesis results. An example VHDL testbench is provided for use in a suitable VHDL simulator. The compilation order of the source code is as follows: 1.2 Cosmetic changes to the source code 02/07/2018 Updated results for Xilinx 7-series 1. ieee div shiftsub.vhd 2. ieee div pipe.vhd 3. ieee div.vhd 4. ieee div bench.vhd The simulation must be run for at least 2 ms during which time an input stimulus of randomized floating-point numbers will generated at the divider input. The simulation generates two text files called: ieee div in.txt and ieee div out.txt. These files respectively capture the input and output floating-point numbers during the course of the test. Copyright 2018 www.zipcores.com Download this IP Core Page 2 of 2