FIR DEC N Half-band Nyquist Decimation Filter Rev. 1.2 Key Design Features Block Diagram Synthesizable, technology independent VHDL Core Half-band polyphase decimation filter with a configurable N decimation factor from 2 to 2 FIR filter core implemented as an optimized 48-tap systolic array (24-taps per phase) for ultimate speed and minimal resource use Configurable data and coefficient widths Symmetric arithmetic rounding limits DC-bias problems Saturation of output samples - no wrap Ships with 14-bit coefficients giving 80 dB stop-band attenuation Only 12 H/W multipliers used per decimate-by-2 stage Supports input sample rates of up to 300 MHz+ Applications Figure 1: Decimation Filter Architecture Decimation of signals after digital-down-conversion N General Description Decimation by a wide range of factors from 2 to 2 Reduction of input sample rate to make subsequent signal FIR DEC N is a polyphase decimation filter that permits the down- processing easier sampling of an input signal by any power of 2. The filter core is organized as a highly optimized systolic array, allowing the user to specify very large decimation factors while keeping resource costs to a minimum. Generic Parameters Input data is sampled on the rising clock-edge of clk when en is active high. Internally, the samples are filtered and decimated then presented at Generic name Description Type Valid range the output interface, y out. num stages Number of decimate- integer 1 The output signal en out is the output clock-enable signal that indicates by-2 filter stages (N) when an output sample is valid. For instance, when decimating by a dw Width of input/output integer 2 factor of 2, then en out will have a duty cycle of 50% relative to the input clock-enable signal. When decimating by a factor of 4, the duty cycle will data samples be 25% and so on. cw Width of coefficients integer 2 fw Number of coefficient integer 0 Filter coefficients and I/O specification fraction bits (fw < cw) 1 Filter coefficients are defined as signed fixed-point numbers in cw fw Pin-out Description format where cw is the total number of coefficient bits and fw is the number of bits in the fractional part. In all cases, cw must be at least 2 bits and fw must be less than cw to accommodate the sign bit. For Pin name I/O Description Active state instance, a coefficient in 10 8 format would be arranged as follows: clk in System clock (F ) rising edge S reset in System reset low en in Clock enable in high en out out Clock enable out high x in in Input samples data (signed number) 1 The design is supplied with Matlab scripts for the easy generation of y out out Decimated output samples data different coefficient sets using FDAtool. Please see application (signed number) note: app note zc002.pdf for more details. Copyright 2011 www.zipcores.com Download this VHDL Core Page 1 of 4FIR DEC N Half-band Nyquist Decimation Filter Rev. 1.2 The standard design ships with 14-bit coefficients in 14 13 format. This coefficient set is sufficient to obtain up to 80dBs of stop band attenuation with a 48-tap half-band filter. Using coefficients with a fewer number of bits will result in a smaller design, but will also compromise filter 2 performance . The number of bits in the input and output samples is controlled by the parameter dw. Inputs and outputs are signed values (their format is purely relative). Sampling frequency considerations The system clock frequency is the sampling frequency of the internal filter core. This is the same as the input sample rate. The sample rate of the output data is a function of the input sampling frequency, F , and the S decimation factor, N, where: F S F (atoutput)= Figure 3: Impulse response 48-tap half-band Nyquist filter S N where , num stages N =2 Filter characteristic Each decimate-by-2 filter section is a 48-tap half-band Nyquist filter with 24-taps per phase. The magnitude response, impulse response and step response of the filter are shown in Figures 2, 3 and 4. Figure 4: Step-response - 48-tap half-band Nyquist filter Functional Timing Figure 5 shows a sequence of input and output samples for a decimation nd factor of 2. Notice that output samples are valid every 2 clock cycle. Outputs should be sampled on the rising clock-edge of clk when en out is active high. Figure 2: Magnitude response 48-tap half-band Nyquist filter 2 We recommend that the parameters in the filter package are left Figure 5: Timing waveform - downsample by 2 alone without modification. If the user requires a different filter response, then please contact Zipcores for advice. Copyright 2011 www.zipcores.com Download this VHDL Core Page 2 of 4