TPG Video Test Pattern Generator Rev. 1.4 Key Design Features Block Diagram Synthesizable, technology independent IP Core for FPGA, reset ASIC and SoC Supplied as human-readable VHDL (or Verilog) source code tpg intl pixout (RGB) Test patterns generated as 24-bit RGB-video 24 tpg wait 16 pixout field 16 16 Supports all video resolutions up to 2 x 2 pixels tpg mode 2 pixout vsync tpg type Progressive and interlaced formats 3 pixout hsync VIDEO tpg width TEST Colour, greyscale or monochrome outputs 16 pixout val PATTERN tpg log2w 4 GENERATOR pixout rdy Bars, squares, lines and bouncing ball display tpg ppl 16 Programmable pattern width and line spacing tpg lpf 16 Simple valid-ready output flow control clk Fully configurable output video resolution Output pixels generated at 1 pixel/clock Figure 1: Video test pattern generator Compatible with all Zipcores video IP cores Pin-out Description cont ... Applications Pin name I/O Description Active state Digital video testing and prototyping pixout 23:0 out 24-bit pixel out data Standard reference video outputs pixout field out Field out 0: even 1: odd Simple screen savers pixout vsync out Vertical sync out high pixout hsync out Horizontal sync out high Pin-out Description pixout val out Output pixel valid high pixout rdy in Ready to accept output high Pin name I/O Description Active state pixel (handshake signal) clk in Synchronous clock rising edge reset in Asynchronous reset low General Description tpg intl in Select interlaced or 0: progressive progressive video 1: interlaced The VIDEO TEST PATTERN GENERATOR IP Core (Figure 1) is a 16 tpg wait 15:0 in Start-up wait time before < 2 (specified versatile test pattern generator capable of producing a range of video test output video is generated in clock cycles) patterns in colour, greyscale and monochrome formats. The module is tpg mode 1:0 in Test pattern colour mode 0: monochrome invaluable during the prototyping of digital video systems. Its also ideal 1: greyscale for any video project that requires a reference video source. 2: colour Pixels and syncs are generated on a rising clock-edge when pixout val is tpg type 2:0 in Test pattern type 0: bars high and pixout rdy is high. The signal pixout vsync is active high when 1: squares the first pixel of a frame is output. The signal pixout hsync is active high 2: hatch when the first pixel of a line is output. The pixout field flag indicates 3: bouncing ball either an odd or even field when interlaced mode is enabled. 4: swap 5: bluescreen By enabling or disabling the pixout rdy signal, the flow of pixels out of the 16 test pattern generator may be easily controlled by the downstream tpg width 15:0 in Test pattern feature width < 2 module. The test pattern generator has infinite video bandwidth. In (must be a other words, the generation of output pixels is only limited by the system power of 2) pixel clock frequency. 4 tpg log2w 3:0 in Log2 (tpg width) < 2 The video output resolution is controlled by the parameters tpg ppl and 16 tpg pll 15:0 in Number of pixels per line < 2 tpg lpf. The colour, type and dimensions of the test pattern are 16 determined by the parameters tpg intl, tpg mode, tpg type, tpg width tpg lpf 15:0 in Number of lines per frame < 2 and tpg log2w. Copyright 2018 www.zipcores.com Download this IP Core Page 1 of 4TPG Video Test Pattern Generator Rev. 1.4 Test pattern dimensions In summary, the bar display is a series of vertical bars that extend the width of the display. The width of the bars is determined by the parameter tpg width. The checker-board display is a series of squares, By controlling the parameters tpg ppl and tpg lpf, the output video with the width of each square controlled by tpg width. The hatch test resolution may be set. The parameters tpg width and tpg log2w control pattern features a number of horizontal and vertical lines of 1 pixel in the width or spacing of the bars, squares or lines. Setting tpl intl to 1 will width. In this instance, the spacing between lines is controlled by generate half the number of lines per frame in order to emulate an tpg width. The bouncing ball test pattern is an animated ball that interlaced video test pattern. bounces randomly and at varying speeds. The ball test pattern is useful for detecting movement artefacts such as motion blur and mouseteeth in As an example, when tpg type is set to bars , tpg width is set to 32 and interlaced video systems. Finally test patterns 4 & 5 (not shown) are plain tpg log2w is set to 5 , then Figure 2 shows the resulting output display. full-screen displays. Type 5 is a constant bluescreen whereas type 4 swaps between blue and yellow on consecutive frames or fields. Functional Timing Pipeline stall clk pixout Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel 4 pixout field pixout vsync pixout hsync pixout val pixout rdy Start of new frame and new line Figure 4: Waveform showing first pixel of a new (progressive) frame Figure 2: Test pattern dimensions RGB output pixels are sampled according to the valid-ready pipeline 1 protocol . Figure 4 shows the signalling at the output of the test pattern Test pattern mode and type generator at the start of a new frame. The first pixel of a new frame begins with pixout vsync and pixout hsync asserted high together with the first pixel. The first pixel of a new line begins with pixout hsync By modifying the text pattern mode and type, the colour and appearance asserted only. of the test pattern may be controlled. Figure 3 shows the types of test pattern available. After reset, and after the start up wait time has been satisfied, valid output pixels are generated. Pixels may be held off by asserting pixout rdy low. As an example, the diagram shows what happens when pixout rdy is de- asserted for one clock cycle. In this case, the output pixels (and syncs if present) are stalled until the ready signal is asserted again. Figure 3: Different test pattern types and colours 1 See application note: app note zc001.pdf on the Zipcores website for more examples of the valid-ready pipeline protocol Copyright 2018 www.zipcores.com Download this IP Core Page 2 of 4