TONE DEC Precision Tone Decoder Rev. 1.3 Key Design Features Block Diagram Synthesizable, technology independent VHDL IP Core reset mag out 16 16-bit signed input and output data samples I i in i out LPF 16 16 Accepts either complex or real inputs q in LEVEL tone present (optional) 16 MAG DETECT COMPLEX Precision Digital Down Converter with 80 dB SFDR en DIGITAL DOWN Q clk CONVERSION LPF q out 32 DDS Frequency resolution of F / 2 S 16 12 32 32 DDS Phase resolution of 2pi / 2 filter type threshold Programmable tone centre frequency and detection bandwidth Detection bandwidth range from 0.005 to 0.03 x F S Choice of low pass filter responses Figure 1: Tone decoder architecture 1 Typical FPGA sample rates of up to 200 MHz Pin-out Description Applications Pin name I/O Description Active state Touch tone decoding (e.g. DTMF tones) clk in Sample clock rising edge reset in Asynchronous reset low Precision frequency monitoring and control en in clock enable high Complex digital down conversion phase inc 31:0 in Phase increment as an data unsigned 32-bit number FSK / OOK / ASK demodulation (controls tone centre frequency) i in 15:0 in Real (In-phase) input data data Generic Parameters samples as a 16-bit signed number Generic name Description Type Valid range q in 15:0 in Imaginary (Quadrature) data input data samples as a gain Internal gain setting integer 0: x 1 16-bit signed number (compensates for low 1: x 2 amplitude input 2: x 4 i out 15:0 out Output data samples as a data signals) 3: x 8 16-bit signed number dithering Enable phase boolean TRUE / FALSE q out 15:0 out Output data samples as a data dithering in DDS 16-bit signed number component mag out 15:0 out Magnitude of complex data 32 seed Seed for random std logic 0 < seed < 2 output number generator in vector tone present out Tone present flag high DDS component use complex Enable complex or boolean TRUE: real data samples use ports i in General Description and q in FALSE: TONE DEC is a precision tone decoder with the capacity to support use port i in either real or complex data samples. Samples are first mixed-down to only baseband before subsequent filtering and tone detection. Figure 1 shows the basic architecture and signal paths. filter type Low-pass filter integer 0: min B/W response type 3: max B/W The centre frequency of the tone is fully programmable and is generated threshold Tone detect threshold integer 0 to 65535 by a local oscillator (DDS). The DDS has an SFDR of better than 80 dBs (with phase dithering) and a theoretical SNR of approximately 100 dBs. 1 Xilinx Virtex 6 FPGA used as a benchmark Copyright 2015 www.zipcores.com Download this VHDL Core Page 1 of 4 gain seed dithering phase inc use complexTONE DEC Precision Tone Decoder Rev. 1.3 After down-conversion, the I and Q signal paths are filtered to remove components above the tone of interest. The characteristics of these filters may be changed depending on the desired detection bandwidth and response time. Finally, a power function is used to compute the relative magnitude of the signal after filtering. If the complex input signal contains the tone of interest, then the relative output magnitude, mag out, will be greater. The generic parameter threshold, is a 16-bit unsigned integer that generates the tone present flag when the magnitude has reached a sufficient level. Tone centre frequency The frequency of the local oscillator is controlled by the signal phase inc. The phase increment may be calculated using the formula: 32 =(F 2 )/ F INC OUT S Where FOUT is the desired waveform output frequency and FS is the sampling frequency. Note that an integer value for the phase increment must be used. As an example, consider a 100 MHz sample clock with a desired local oscillator frequency of 6.197 MHz. The phase increment 32 would be calculated as (6.197 * 2 ) / 100 + 0.5 = 266159123. The minimum and maximum local oscillator frequencies are given by the following formulas: 32 , F =F /2 F = F /2 MAX S MIN S As an example, a 100 MHz sample clock would allow a minimum local oscillator frequency of 0.0233 Hz. Conversely, the maximum frequency the local oscillator can generate is given by the Nyquist / Shannon sampling theorem (F / 2). S Low pass I/Q filters After digital down conversion, the I and Q paths are filtered using a pair of IIR filters. Note that as these filters are recursive in nature, then the resulting output phase is non-linear. This must be taken into consideration if subsequent signal processing is to be done on the Figure 2: Low-pass filter responses. The -3dB cutoff points are: complex outputs. (a) 0.005, (b) 0.001, (c) 0.02 and (d) 0.03 rads/sample In total, there are four separate filter responses that may be selected using the generic parameter filter type. Figure 2 shows the different filter Note that it is important that the full 16-bit dynamic range of the tone responses for each setting. decoder inputs is used in order for the low-pass filters to function optimally. For input samples with lower numbers of significant bits, the Filter (a) is characterized by a very narrow bandwidth and a long impulse generic gain parameter may be adjusted accordingly. response time. Conversely, filter (d) has a much wider bandwidth with a shorter response time. The table below outlines these parameters in more detail. Functional Timing Filter type -3dB cutoff frequency Approximate Figure 3 shows the operation of the tone decoder during normal Response time operation. In this particular example, the threshold has been set to 0x400 and use complex has been set to false. This means that only the I 0 : (a) 0.005 * (FS / 2) 300 samples signal path is used with Q unused. 1: (b) 0.01 * (F / 2) 150 samples S Notice that the tone present flag is asserted high when the output 2 : (c) 0.02 * (F / 2) 75 samples S magnitude exceeds the threshold. The threshold value may be adjusted in order to alter the sensitivity of detection circuit. This may be necessary 3 : (d) 0.03 * (FS / 2) 50 samples depending on the input signal dynamic range and the chosen filter type. The waveforms also show the action of the clock-enable signal en. Copyright 2015 www.zipcores.com Download this VHDL Core Page 2 of 4