ATAN2 XY 12-bit 4-Quadrant Arctan Function Rev. 1.2 Key Design Features Block Diagram Synthesizable, technology independent VHDL IP Core Function = atan2 (y,x) Inputs as 12-bit signed numbers Output phase as a 19-bit signed Output range - Option for scaled output phase in range -1 1 Figure 1: 4-quadrant Arctan core architecture Accurate to within 0.00008 radians General Description High-speed fully pipelined architecture ATAN2 XY (Figure 1) calculates the 4-quadrant inverse tangent in the Small implementation size range - to . It has a fully pipelined architecture and uses fixed-point mathematics throughout. Input values are accepted as 12-bit signed 7 clock-cycle latency numbers in the range -2048 to 2047. The calculated output phase (in radians) is a 19-bit signed value with 1 sign bit, 2 integer bits and 16 fractional bits. As an example, the output phase angle 0x18000 would Applications represent 1.5 radians and the value 0x68000 would represent the value nd -1.5 radians. Internally, the arctan core function uses a 2 order polynomial of the form: Fixed-point mathematics 2 Precision phase measurements in digital communications and y= ax bx c digital signal processing Digital Phase-locked Loops (PLLs) The coefficients a, b and c dynamically change with respect to the input value in order to generate a more accurate approximation. The output More accurate, smaller, lower latency and faster than a result is accurate to within 0.00008 radians. Values are sampled on the CORDIC solution of similar specification rising clock-edge of clk when en is high. The function has a 7 clock-cycle latency in normal operation and 9 clock-cycles when the scaled phase output is selected. Pin-out Description Scaled phase output option Pin name I/O Description Active state clk in Synchronous clock rising edge By default, the output phase angle is computed in radians in the range -Pi to Pi. This is specified by setting the generic parameter scale output = en in Clock enable high false. Alternatively, by setting the generic parameter: scale output = true, the output phase angle is generated in the range -1 to 1. The two options x in 11:0 in Input value data are described graphically in Figure 2 below. y in 11:0 in Input value data phi out 18:0 out Output phase angle in data radians Functional Specification Value Type Valid range x in 11:0 12-bit signed number -2048, 2047 y in 11:0 12-bit signed number -2048, 2047 phi out 18:0 19-bit signed fraction in 19 16 format -, Accurate to within Figure 2: Output phase angle options: 0.00008 (a) scale output = false, (b) scale output = true radians Copyright 2014 www.zipcores.com Download this VHDL Core Page 1 of 3ATAN2 XY 12-bit 4-Quadrant Arctan Function Rev. 1.2 The simulation must be run for at least 2 ms during which time a Functional Timing randomized 2 x 12-bit input stimulus will be generated at the input to the arctan core. The test terminates automatically. Figure 3 demonstrates a series of computations of = atan2 (y,x). The simulation generates two text files called atan2 xy in.txt and Samples are processed on the rising edge of clk when en is high. The atan2 xy out.txt. These files contain the input and output samples function has a 7 cycle latency as shown by the timing between edges A captured during the course of the test and may be used to verify the and B in the waveform. correct operation of the core. In the example, the first calculation is = atan2(0x02C,0x07E), the next calculation is = atan2(0xEB7, 0x98D). The results are respectively 0x05601 and 0x50E1B. Converting the numbers to decimals and decimal Performance fractions the calculations are equivalent to: Quadrature samples were generated in the range - to in order to =atan244,126=0.335953 check the accuracy and linearity of the phase output. Quadrature samples were generated according to the formulas: and .. =atan2329,1651=2.944901 x= Gcos() y=Gsin() Note that the clock-enable is held low for one clock cycle during the second sample during which the whole pipeline is stalled. Where is a phase angle in the range -, and G is a scale factor. The generated x, y samples were used as an input stimulus to the ATAN2 XY core and the output samples were captured during the simulation. Figure 4 shows the resulting plot of (ideal) input phase vs. output phase in radians. The overall accuracy was measured at 0.00008 radians. This compares with a theoretical best case of 0.000015 radians for a 16-bit fractional output. Figure 3: Timing waveform for the atan2 xy function Source File Description All source files are provided as text files coded in VHDL. The following table gives a brief description of each file. Source file Description lut reciprocal.vhd Reciprocal unit lut divide.vhd Division unit atan2 scale.vhd Phase scaling unit atan2 x.vhd Arctan core function atan2 xy.vhd Top-level block atan2 xy bench.vhd Top-level test bench Functional Testing Figure 4: Plot of Input phase vs. output phase showing good linear relationship An example VHDL testbench is provided for use in a suitable VHDL simulator. The compilation order of the source code is as follows: 1. lut reciprocal.vhd 2. lut divide.vhd 3. atan2 scale.vhd 4. atan2 x.vhd 5. atan2 xy.vhd 6. atan2 xy bench.vhd Copyright 2014 www.zipcores.com Download this VHDL Core Page 2 of 3