UART CONT UART Serial Interface Controller Rev. 2.0 Key Design Features Block Diagram Synthesizable, technology independent IP Core for FPGA, ASIC and SoC tx flag reset Supplied as human-readable VHDL source code. (Verilog translation may be provided on request). UART compatible serial interface controller tx data Receive and transmit input/output FIFOs with configurable TX OUT depth tx val UART TX PAD Supports all standard data rates from 9600 to 921600 baud tx rdy Fully custom data rates also supported - limited only by system clk clock frequency Tx FIFO 5, 6, 7 or 8-bit data payload width with 1 or 2 stop bits Rx FIFO Even, odd, mark, space or no parity rx data Receive and transmit interrupt flags rx err RX IN Rx and Tx FIFO count values and full flags rx val UART RX PAD rx rdy Applications UART communications using a range of electrical standards such as RS232, RS422 and RS485 etc. rx flag Control in industrial, commercial and lab environments Basic PC-to-board interfacing and debug including simple comms using a range of popular USB-to-UART bridge ICs Figure 1: Simplified UART serial interface controller architecture Ideal for micro-controller communications between FPGA and MCU Pin-out Description Generic Parameters Pin name I/O Description Active state Generic name Description Type Valid range clk in Synchronous clock rising edge 6 sclkfreq System clock integer 10 reset in Asynchronous reset low frequency in Hz baudrate 3:0 in Baud rate setting 0000: 2400 rxfifo depth Receive data FIFO integer 2 0001: 4800 depth (All common baud rates 0010: 7200 are supported up 921600 0011: 9600 rxfifo depth log2 Receive data FIFO integer log2 baud. Other baud rates depth log2 (rxfifo depth) supported on request. Not 1110: 460800 all baud rates are shown 1111: 921600 (Used to help with here) synthesis only) databits 1:0 in Number of data bits 00: 5 data bits txfifo depth Transmit data FIFO integer 2 01: 6 data bits depth 10: 7 data bits 11: 8 data bits txfifo depth log2 Transmit data FIFO integer log2 depth log2 (txfifo depth) stopbits in Number of stop bits 0: 1 stop bit 1: 2 stop bits (Used to help with synthesis only) parity 2:0 in Parity setting 000: None 001: Even 010: Odd 011: Mark 100: Space Copyright 2020 www.zipcores.com Download this IP Core Page 1 of 5 FIFO stage n FIFO stage 0 rx count FIFO stage 1 rx full tx count FIFO stage 1 tx full FIFO stage 0 FIFO stage nUART CONT UART Serial Interface Controller Rev. 2.0 Both the transmit and receive FIFOs have an external counter signal Pin-out Description cont ... called tx count and rx count. These counter values are updated on every clock cycle and indicate the number of occupied entries in the respective FIFOs. The counter values may be used to determine how full Pin name I/O Description Active state or empty the FIFOs are at any time. rx flag out Data received flag high rx full out Receive FIFO full flag high Programmable UART parameters rx count out Receive FIFO counter data value (fullness) The baud rate setting, number of data bits, number of stop bits and parity tx flag out Data transmitted flag high bits may be programmed in real-time. After changing any of the UART parameters, it is recommended that a system reset is performed. This is tx full out Transmit FIFO full flag high done by asserting the reset signal low for at least 2 system clock cycles. tx count out Transmit FIFO counter data 2 A full list of baudrate settings is shown below : value (fullness) rx in in Serial bits in serial data 0000: baudrate = 2400 tx out out Serial bits out serial data 0001: baudrate = 4800 rx data 7:0 out Received data data 0010: baudrate = 7200 0011: baudrate = 9600 rx err out Parity error flag high 0100: baudrate = 14400 (qualified by rx val) 0101: baudrate = 19200 0110: baudrate = 28800 rx val out Received data valid high 0111: baudrate = 33600 rx rdy in Received data ready high 1000: baudrate = 38400 handshake 1001: baudrate = 57600 1010: baudrate = 115200 tx data 7:0 in Transmit data data 1011: baudrate = 128000 tx val in Transmit data valid high 1100: baudrate = 230400 1101: baudrate = 256000 tx rdy out Transmit data ready high 1110: baudrate = 460800 handshake 1111: baudrate = 921600 General Description Functional Timing The UART CONT IP Core is a robust UART-compliant serial interface Figure 2 shows the format of the bit stream at the UART receiver. The controller capable of receiving and transmitting bits serially. It has a example demonstrates the timing waveform at 9600 baud in which the configurable data payload from 5 to 8-bits (with or without parity) and duration of a bit is approximately 104 us. supports either 1 or 2 stop bits. A frame begins with a START bit (logic 0 ) then the bits are read starting Both the receiver and transmitter circuits have a configurable FIFO which with the LSB and ending with the MSB. The frame terminates with a may be used to buffer the parallel input and output data as required. In STOP bit (Logic 1 ). The design may be configured to use 5, 6, 7 or 8 addition, the controller features a number of flags and counters to indicate data bits, an optional parity bit and 1 or 2 stop bits. the state of the FIFOs and also whether a data word has been received or sent. In the standard configuration, the controller will support baud rates from 2400 to 921600 baud, although higher and lower rates may be supported depending on the choice of system clock frequency. Fully custom baud rates may also be implemented on request. RX IN 104 us Start Parity Stop Stop The UART controller is comprised of four main blocks as described by D0 D1 D2 D3 D4 D5 D6 D7 Bit Bit Bit 1 Bit 2 Figure 1. These blocks are the receiver (de-serializer), the transmitter (serializer) and the receive and transmit FIFOs. 5 data bits (optional) (1 or 2 stop bits) 6 data bits Both the receive and transmit FIFOs use a simple data streaming protocol 7 data bits 8 data bits with a valid/ready handshake. Data is written or read from the FIFOs on 1 the rising-edge of clk when val and rdy are both high . Figure 2: UART serial bitstream format The transmit FIFO may be used to queue up a sequence of bytes to be sent via the UART interface. Likewise, the receive FIFO may be used to buffer incoming bytes. When the receive FIFO is full the flag rx full is asserted and will remain high until the FIFO is emptied. If the receive FIFO is full, then any further bytes received will be lost until the FIFO has sufficient capacity. 1 Please see Zipcores application note: app note zc001.pdf for more 2 Other baud rates (custom or otherwise) may be supported on request. examples of how to use the valid-ready pipeline protocol. Please contact Zipcores for more information. Copyright 2020 www.zipcores.com Download this IP Core Page 2 of 5