SKU25 Zipcores

I2C SLAVE I2C Slave Serial Interface Controller Rev. 2.0 Key Design Features Block Diagram CONFIG Synthesizable, technology independent IP Core for FPGA and reset REGISTERS ASIC (read/write) address Config reg n Supplied as human readable VHDL (or Verilog) source code 8 write data Phillips I2C-bus compliant 8 8 PAD User defined I2C slave address Config reg 2 config Config reg 1 scl 8 Configurable number of 8-bit read/write configuration registers Config reg 0 oe up to a maximum of 128 I2C SLAVE read PAD CONTROLLER data READ Status reg n MUX Configurable number of 8-bit read-only status registers up to a sda maximum of 128 Features standard I2C register addressing common to most I2C 8 peripherals Status reg 2 status Status reg 1 clk Fully configurable clocking allows Standard (100kHz), Fast Status reg 0 (400kHz) and custom data rates exceeding 20 MHz STATUS REGISTERS Compatible with a wide range of I2C master devices such as (read only) Micro-controllers and COTs ICs Applications Figure 1: I2C slave serial interface controller architecture I2C slave communication Generic Parameters Inter-chip board-level communications Standard 2-wire comms between a wide range of I2C Generic name Description Type Valid range peripherals, micro-controllers and COTs ICs. num config Number of integer 2 regs 128 configuration registers Pin-out Description num status Number of integer 2 regs 128 Status registers slave address 8-bit slave address of std logic 0000000X Pin name I/O Description Active state the device on the I2C vector to bus (LSB is don t care) 1111111X clk in Synchronous clock rising edge reset in Asynchronous reset low scl in I2C input SCL clock pin as per I2C General Description specification sda i/o I2C bi-directional SDA as per I2C The I2C SLAVE IP Core is a Philips I2C compliant slave interface data pin specification controller. The controller decodes the SCL and SDA bus signals and ad flag out Address register write flag pulse high converts them into a simple series of 8-bit read/write commands for accessing a set of user-defined registers. These registers are defined as wr flag out Config register write flag pulse high either configuration registers or status registers. rd flag out Config register read flag pulse high Config registers provide general purpose read/write bits for the control of ro flag out Status register read flag pulse high external logic. Status registers are read-only and allow the state of external pins to be monitored via the I2C interface. Both the config and config out Configuration register data status bits are visible at the controller top-level ports. num config*8 - 1:0 output bits status in External status register data The SCL port is an input driven by the I2C Master. The SDA port is num status*8 - 1:0 input bits connected to a bi-directional tristate buffer. When the I2C controller is inactive, both the SCL and SDA lines will be in a high impedance (high-Z) state. Note: The SCL and SDA pins should have external (or internal) pullups as per the I2C specification. Copyright 2015 www.zipcores.com Download this VHDL Core Page 1 of 4 ad flag wr flag rd flag ro flagI2C SLAVE I2C Slave Serial Interface Controller Rev. 2.0 The I2C slave controller is comprised of three main blocks as described by Figure 1. These blocks are the I2C Slave Controller core the Configuration register bank and the Status register bank. I2C Slave Controller Core The slave controller core is a state-machine that continually monitors the state of the SCL and SDA lines and generates the appropriate signals on the I2C bus. In order for the slave to function correctly the system clock frequency to SCL clock frequency must have a ratio of 8:1 or greater. That is, the following formula must be satisfied such that: f f 8 CLK SCL f = systemclock frequency(Hz) CLK f = I2Cclock frequency(Hz) SCL To begin a data transfer, the state machine looks for a start command which is defined by a stable SCL high signal with a falling SDA line. On receipt of a start command, the slave will latch the slave address and the r/w flag over the next eight consecutive bits. If the slave address on the bus corresponds to the generic parameter slave address, then the controller will generate an acknowledge signal and a data transfer may commence. If the slave address mismatches, then the controller will not acknowledge the master and it will revert back to it s idle state waiting for the next start condition. Once the controller has been addressed correctly, the master may send one of two possible commands to the slave. These commands are either a register write or a register read. The I2C command sequences understood by the slave controller are summarized by Figure 2 opposite. Configuration and Status Register banks The number of configuration registers accessible by the slave controller is specified in the generic parameter num config. Likewise, the number of status registers is specified in the num status generic. Configuration registers are read/write addressable, while status registers are read-only. Both types of registers are 8-bits wide with a maximum of 128 registers in each bank. The type of register accessed is determined by the MSB of the register address that is latched in the I2C command sequence (see Figure 2). This means that the addresses from 0x00 to 0x7F access the configuration register bank and the addresses from 0x80 to 0xFF are the status register bank. If the I2C master writes to a register address that doesn t exist then nothing will happen. Reading a register that doesn t exist will result in the value 0xFF being returned on the I2C bus. Figure 2: I2C command sequence for a register byte write and a register byte read Copyright 2015 www.zipcores.com Download this VHDL Core Page 2 of 4 ACK from Slave A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 REGISTER WRITE SEQUENCE STRT SLAVE ADDRESS 0 ACK C/S REGISTER ADDRESS ACK REGISTER WRITE DATA ACK STOP 0 = Config register R/W = 0 1 = Status register ACK from Slave REGISTER READ SEQUENCE STRT SLAVE ADDRESS 0 ACK C/S REGISTER ADDRESS ACK 0 = Config register R/W = 0 1 = Status register RPT NO SLAVE ADDRESS 1 ACK REGISTER READ DATA STOP STRT ACK NO-ACK from Master R/W = 1