XY SCALER Digital Video Scaler IP Core Rev. 3.1 Key Design Features Block Diagram Synthesizable, technology independent soft IP Core for FPGA, ASIC and SoC devices bypass en reset Supplied as human readable VHDL (or Verilog) source code Versatile RGB (or YCbCr 444) video scaler capable of scaling PIXEL BUFFER LINE BUFFER up or down by any factor RGB or YCbCr RGB or YCbCr tap0 tap1 dw*3 dw*3 Fully programmable scale parameters and scaler bypass pixin tap2 pixout function tap3 pixin vsync pixout vsync tap4 Fully programmable RGB channel widths allow support for any pixin hsync RGB format (or greyscale if only one channel is used) pixout hsync 5-TAP 5-TAP POLYPHASE POLYPHASE pixin val 16 16 pixout val Supports all video resolutions up to 2 x 2 pixels FILTER FILTER pixin rdy COEFFICENT COEFFICENT pixout rdy Fully pipelined architecture with simple data-streaming flow ROM ROM control HORIZONTAL VERTICAL clk SCALER SCALER Features a 5x5-tap polyphase filter in the x and y dimensions with 16 unique phases 24 24 16 16 16 16 Example general purpose Lanczos2 filter coefficients shipped with the design. Different coefficient sets available on request Output rate is 1 x pixel per clock for scaling factors > 1 Generates one scaled output frame for every input frame No frame buffer required Figure 1: Digital video scaler architecture 1 Supports 350MHz+ operation on basic FPGA devices Pin-out Description Applications Pin name I/O Description Active state Studio quality dynamic real-time video scaling clk in Synchronous clock rising edge reset in Asynchronous reset low Conversion of all standard and custom video resolutions such as HD720P to HD1080P, XGA to VGA etc. bypass en in Bypass the video scaling 0: scaled video function 1: bypass video Support for the latest generation video formats with resolutions scale pitch x 23:0 in 1 / (x scale factor) data of 4K and above (Unsigned number in 24 12 format) Video scaling for flat panel displays, portable devices, video image sensors, consoles, video format converters, set-top scale pitch y 23:0 in 1 / (y scale factor) data boxes, digital TV etc. (Unsigned number in 24 12 format) Picture-in-Picture (PiP) and dynamic zoom applications input ppl 15:0 in Number of pixels per line in data the source video (Unsigned 16-bit number) Generic Parameters input lpf 15:0 in Number of lines per frame data in the source video Generic name Description Type Valid range (Unsigned 16-bit number) dw RGB channel width integer 2 output ppl 15:0 in Number of pixels per line in data the scaled output video 4 16 line width Width of linestores in integer 2 < pixels < 2 (Unsigned 16-bit number) pixels output lpf 15:0 in Number of lines per frame data log2 line width Log of linestore width integer Log 2 2 in the scaled output video (line width) (Unsigned 16-bit number) 1 Xilinx 7-series used as a benchmark Copyright 2020 www.zipcores.com Download this IP Core Page 1 of 5 tap0 scale pitch x tap1 scale pitch y tap2 tap3 input ppl tap4 input lpf output ppl output lpf line width log2 line widthXY SCALER Digital Video Scaler IP Core Rev. 3.1 As an example, consider the scaling of VGA format video (640x480) to Pin-out Description cont ... XGA format video (1024x768). In this case the scale pitch in the x and y dimensions would be 0.625. As the value must be specified as a 12.12- 12 bit number the actual scale pitch must be multiplied by 2 giving the Pin name I/O Description Active state value 2560 . pixin dw*3 - 1:0 in RGB pixel in data In addition the user must also specify the exact resolution of the source pixin vsync in Vertical sync in high input frame and the scaled output frame using the parameters: input ppl, (Coincident with first pixel input lpf, output ppl and output lpf. The following tables give a list of of input frame) generic parameters required for the conversion of some example video formats. pixin hsync in Horizontal sync in high (Coincident with first pixel of input line) SCALE UP pixin val in Input pixel valid high Video Video Pitch Pitch I/P I/P O/P O/P IN OUT X Y PPL LPF PPL LPF pixin rdy out Ready to accept input pixel high (Handshake signal) VGA SVGA 3277 3277 640 480 800 600 640x480 800x600 pixout dw*3 - 1:0 out RGB pixel out data SVGA XGA 3200 3200 800 600 1024 768 pixout vsync out Vertical sync out high 800x600 1024x768 (Coincident with first pixel of output frame) XGA HD1080 2184 2913 1024 768 1920 1080 1024x768 1920x1080 pixout hsync out Horizontal sync out high (Coincident with first pixel SXGA 2K 2560 3884 1280 1024 2048 1080 of output line) 1280x1024 2048x1080 pixout val out Output pixel valid high pixout rdy in Ready to accept output high SCALE DOWN pixel Video Video Pitch Pitch I/P I/P O/P O/P (Handshake signal) IN OUT X Y PPL LPF PPL LPF SVGA VGA 5120 5120 800 600 640 480 800x600 640x480 General Description XGA SVGA 5243 5243 1024 768 800 600 1024x768 800x600 The XY SCALER IP Core is a studio quality video scaler capable of 16 16 generating interpolated output images from 16 x 16 up to 2 x 2 pixels HD1080 XGA 7680 5760 1920 1080 1024 768 in resolution. The architecture permits seamless scaling (either up or 1920x1080 1024x768 down) depending on the chosen scale factor. Internally, the scaler uses a 2K SXGA 6554 4320 2048 1080 1280 1024 24-bit accumulator and a bank of polyphase FIR filters with 16 phases or 2048x1080 1280x1024 interpolation points. All filter coefficients are programmable, allowing the user to define a wide range of filter characteristics. Flow control Pixels flow into and out of the video scaler in accordance with a simple valid-ready streaming protocol. Pixels are transferred into the scaler on a rising clock-edge when pixin val and pixin rdy are both active high. Pixels flow in and out of the video scaler in accordance with the valid- Likewise, pixels are transferred out of the scaler on a rising clock-edge 2 ready pipeline protocol . The scaling operation occurs on a line-by-line when pixout val and pixout rdy are both active high. As such, the basis with the signal pixin hsync specifying the start of a new line and pipeline protocol allows both input and output interfaces to be stalled independently. pixin vsync specifying the start of a new frame. All pixels into the scaler (including pixin vsync and pixin hsync) must be qualified by the pixin val signal asserted high, otherwise changes to the input signals will be The scaler is partitioned into a horizontal scaling module in series with a ignored. Note that the first pixel of a new frame is accompanied by a valid vertical scaling module as shown by Figure 1. vsync and hsync. The first pixel in a new line is accompanied by hsync only. Scale pitch, pixels per line and lines per frame On receipt of the first vsync, the scaling operation begins and output pixels are generated in accordance with the chosen scale parameters. Generally, for scale-down (decimation) operations, the input interface will The output resolution of the scaled output image is controlled by the generic parameters scale pitch x, scale pitch y, input ppl, input lpf, not stall. Conversely, for scale-up (interpolation) the number of output pixels will be greater than the number of input pixels. This will result in output ppl and output lpf. The scale pitch may be calculated using the the occasional stalling of the input due to the change in ratio. following formula: Input resolution 12 pitch=( ) 2 Output resolution 2 See Zipcores application note: app note zc001.pdf for more examples of how to use the valid-ready pipeline/streaming protocol Copyright 2020 www.zipcores.com Download this IP Core Page 2 of 5