FIR NTAP Generic ultra-speed FIR Filter Rev. 1.2 Key Design Features Block Diagram Synthesizable, technology independent VHDL Core Implemented as a systolic array for speed and scalability Configurable coefficients, data width and number of taps Symmetric arithmetic rounding limits DC-bias problems Output saturation or wrap modes Figure 1: FIR filter architecture (Simplified) 1 Supports 550 MHz+ sample rates General Description Applications FIR NTAP is an FIR filter implementation designed for very high sample rate applications. Organized as a systolic array (Figure 1) the filter is modular and fully scalable, permitting the user to specify large order filters Very high-speed filtering applications without compromising maximum attainable clock-speed. Mathematically, the filter implements the difference equation: General purpose FIR filters with odd or even numbers of taps Filters with arbitrary sets of coefficients (e.g. non-symmetrical) y n = h x n h x n1 ... h x nN 0 1 N Pin-out Description In the above equation, the input signal is x n , the output signal is y n and h0 to hN represent the filter coefficients. The number N is the filter order, the number of filter taps being equal to N+1. Pin name I/O Description Active state 2 Filter coefficients are defined as signed fixed-point numbers in cw fw clk in Sampling clock rising edge format where cw is the total number of coefficient bits and fw is the en in Clock enable high number of bits in the fractional part. In all cases, cw must be at least 2 bits and fw must be less than cw to accommodate the sign bit. For x in dw-1:0 in Filter input samples data instance, a coefficient in 10 8 format would be arranged as follows: (signed number) y out dw-1:0 out Filter output samples data (signed number) Generic Parameters The number of bits in the input and output samples is controlled by the Generic name Description Type Valid range parameter dw. Inputs and outputs are signed values (their format is purely relative). Output samples may be truncated to dw bits or rounded num taps Number of filter taps integer > 2 depending on the implementation option USE ROUNDING. If the dw Width of input/output integer 2 rounding option is selected, then symmetric arithmetic rounding is used. data samples This means that the fraction 0.1000... is added to positive numbers and 0.0111... is added to negative numbers. Note that filters implemented cw Width of coefficients integer 2 with the rounding option will help to reduce the small amplitude offset introduced at DC (0 Hz baseband frequency) attributable to rounding fw Number of coefficient integer 0 fraction bits (fw < cw) error. coeff Filter coefficients integer 0 In addition, the option USE SATURATE determines what will happen if num taps-1:0 array the output samples are too large. If the saturate option is enabled, then in the event of an overflow, the output samples will saturate to the largest USE ROUNDING Use symmetric Boolean TRUE/FALSE positive or negative number permitted by dw. With the saturate option arithmetic rounding disabled, the output samples will simply wrap around. Note that (not truncate) depending on the format of the coefficients and the data width relative to USE SATURATE Saturate outputs Boolean TRUE/FALSE the magnitude of the input samples, the filter outputs may not overflow. In (not wrap) this case, the user may not require the saturation logic. USE OPTZERO Optimize for zero- Boolean TRUE/FALSE valued coefficients 2 The design is supplied with Matlab scripts for the easy generation of coefficient sets using FDAtool. Please see application note: 1 Xilinx Virtex 5 FPGA used as a benchmark app note zc002.pdf for more details. Copyright 2011 www.zipcores.com Download this VHDL Core Page 1 of 3FIR NTAP Generic ultra-speed FIR Filter Rev. 1.2 Finally, the parameter USE OPTZERO determines whether the design Functional Testing should be optimized for coefficients with a value of zero. This will result in a smaller design overall, but may also limit the best attainable clock speed. An example VHDL testbench is provided for use in a suitable VHDL simulator. The compilation order of the source code is as follows: Values are sampled on the rising clock-edge of clk when en is high. The latency of the filter is determined by the formula: 1. fir ntap pack.vhd 2. fir ntap mad.vhd 3. fir ntap mad zero.vhd Lat =Taps Lat Lat 4 TOT RND SAT 4. fir ntap rnd.vhd 5. fir ntap sat.vhd 6. fir ntap.vhd Where Lat is the total latency between the first input sample to enter TOT 7. fir ntap bench.vhd the filter and the first output sample, Taps is the total number of filter taps, Lat is the latency of the rounding block (equal to 2 clock cycles) and RND LatSAT is the latency of the saturation block (equal to 1 cycle). The VHDL testbench instantiates the FIR filter component. The user may modify the generic parameters in the file fir ntap pack.vhd as As an example, consider a 20 tap filter with rounding and saturation required. The test provided is configured for an low-pass equiripple filter enabled. The total latency would be : 20 + 2 + 1 + 4 = 27 clock cycles. with 45 taps. The simulation must be run for at least 1 ms during which time the Functional Timing impulse response and step response of the filter is tested. The simulation generates a text file called fir ntap out.txt that contains Figure 2 shows a sequence of input samples for a 20 tap filter with the output samples captured during the course of the test. Figures 3 and rounding and saturation enabled. Output samples appear 27 clock-cycles 4 respectively contain the impulse response and step response outputs of later. the filter. Figure 2: FIR filter input/output samples Source File Description All source files are provided as text files coded in VHDL. The following table gives a brief description of each file. Note that all generic parameters are defined in the package fir ntap pack.vhd . Source file Description fir ntap pack.vhd Package containing all generic parameters - including coefficients. fir ntap mad.vhd Multiply-Add block Figure 3: Impulse response of the 45-tap low-pass FIR filter fir ntap mad zero.vhd Miltiply-Add block optimized for zero-valued coefficients fir ntap rnd.vhd Rounding block fir ntap sat vhd Saturation block fir ntap.vhd Top-level block fir ntap bench.vhd Top-level test bench Copyright 2011 www.zipcores.com Download this VHDL Core Page 2 of 3