BRIDGE UART I2C UART to I2C Bridge Controller Rev. 1.1 Key Design Features Block Diagram Synthesizable, technology independent IP Core for FPGA, reset ASIC and SoC Supplied as human-readable VHDL (or Verilog) RTL source UART setup I2C setup baudrate device id UART (Master) connects to a standard I2C bus and operates as sclkfreq Write t period stopbits command t data su a fully transparent bridge between the two buses parity I/F timeout FIFO FIFO Support for standard UART data rates between 9600 and Full-duplex buffer buffer Tristate drivers buffers 921600 baud PAD Support for all common I2C bit rates such as 100kbps, PAD 400kbps, 1Mbps and 4Mbps scl rx in UART I2C Simple command interface allows the programming of I2C CONTROLLER CONTROLLER peripherals using a serial terminal program (e.g.TeraTerm, PAD PAD HyperTerminal, PuTTY, YAT etc.) Read tx out sda data I/F Applications FIFO FIFO buffer buffer Convenient method for translating commands between UART and I2C devices and peripherals clk Essential tool for the remote debug of I2C devices using an external PC, micro-processor or mico-controller Figure 1: UART-to-I2C bridge architecture Pin-out Description Generic Parameters Generic name Description Type Valid range Pin name I/O Description Active state baudrate UART baud rate in bits integer 9600 to clk in Synchronous clock rising edge per second 921600 reset in Asynchronous reset low (custom rates also supported) sclkfreq System clock integer Ratio (sclkfreq / rx in in Serial bits in UART serial frequency in Hz baudrate) data < 65536 tx out out Serial bits out UART serial databits Number of data bits integer Set to 8 only data stopbits Number of stop bits integer 1,2 parity Enable parity bit after integer 0: none scl i/o I2C bi-directional SCL As per I2C data payload in 1: even clock pin specification bitstream 2: odd sda i/o I2C bi-directional SDA As per I2C 3: mark 4: space data pin specification timeout UART timeout in integer 2 system clock cycles General Description (must be greater than (but much the time taken to send larger in 32 bits at the current practice) The BRIDGE UART I2C IP Core (Figure 1) provides a simple and baud rate) convenient way to interface a standard UART bus to a standard I2C bus. device id I2C slave device ID integer 2 The circuit operates as a completely transparent bridge between the two buses and allows I2C peripherals to be programmed using a set of basic t period SCL clock period (as integer 2 commands over a (UART) serial interface. number of system clock cycles) Both the UART and I2C transceivers may be configured individually to t data su SDA setup/hold time integer 4 support a wide range of standard and custom settings. The bridge circuit (as number of system is technology independent and may be implemented as a custom ASIC, clock cycles) or using a standard FPGA or SoC. Copyright 2019 www.zipcores.com Download this IP Core Page 1 of 4BRIDGE UART I2C UART to I2C Bridge Controller Rev. 1.1 In particular, the IP Core is ideal for the remote programming of I2C Functional Timing peripherals using a remote PC or micro-controller. This is especially useful during the debug stages of a project when the I2C registers of a device may be written and read with the help of a simple terminal Both the UART and I2C buses implement standard timing waveforms as program. described in the UART and I2C specifications. The timing diagram below gives an example for the command: 0xFF 0x55 0x82 0x6F with the baud rate set to 115200 and the I2C clock set to 100kHz. UART Command Interface The UART command interface consists of 4 consecutive bytes that are used to initiate a read or a write on the I2C bus. Typically, this is used to read or write a register accessed via I2C. An I2C write is initiated by the following command: 0xFF 0x55 0xADDR 0xDATA (Where 0xADDR is the register address to be accessed and 0xDATA is the byte of data to be written). Figure 2 shows the corresponding command that is generated on the I2C bus: I2C DEVICE ID SLAVE WRITE SLAVE WRITE SLAVE START STOP REG ADDRESS REG DATA + R/W = 0 ACK ACK ACK Example: With the I2C device id generic set to 0x40, the UART command: 0xFF 0x55 0x3A 0x72 will generate the following sequence on the I2C bus: <START> <0x40> <ACK> <0x3A> <ACK> <0x72> <ACK> <STOP> Figure 2: I2C write command sequence Similarly, an I2C read is initiated by the following command: 0xFF 0xAA 0xADDR 0xXX (Where 0xADDR is the register address to be accessed and the value of byte 0xXX is dont care). Figure 3 below shows the command that is generated on the I2C bus: I2C DEVICE ID SLAVE WRITE SLAVE START STOP + R/W = 0 ACK REG ADDRESS ACK I2C DEVICE ID SLAVE READ MASTER START STOP + R/W = 1 ACK REG DATA NACK Example: With the I2C device id generic set to 0x40, the UART command: 0xFF 0xAA 0x3A 0x00 will generate the following sequence on the I2C bus: <START> <0x40> <ACK> <0x3A> <ACK> <STOP> <START> <0x41> <ACK> <0xREAD DATA> <NACK> <STOP> Figure 3: I2C read command sequence Note that the I2C slave address device id must be set correctly in the generic parameters so that the correct I2C slave device is accessed on the bus. Another important consideration is to make sure that the UART and I2C generics are set correctly for the desired data rates. In addition, the UART timeout setting should be set appropriately for the given baud rate. For instance, if the baud rate is set to 9600 with 1 stop bit and no parity, then a four byte UART command should take: 10 x 4 / 9600 = approx 4.2 ms. As such, the timeout should be set to greater than 4.2 ms with some margin to compensate for a slow terminal. Copyright 2019 www.zipcores.com Download this IP Core Page 2 of 4 0xFF 0x55 0x82 0x6F 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 1 0 0 0 0 0 1 1 1 1 1 0 1 1 0 UART rx in tx out scl sda I2C 0 1 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 1 1 0 1 1 1 1 0x40 0x82 0x6F START STOP START STOP START STOP START STOP START ACK ACK ACK STOP