SKU101 Zipcores

HD SMPTE TPG High-Definition SMPTE Test Pattern Generator Rev. 1.1 Key Design Features Block Diagram Synthesizable, technology independent IP Core for FPGA, ASIC and SoC reset Supplied as human-readable VHDL (or Verilog) source code Test patterns generated as an industry standard 20-bit 4:2:2 SMPTE stream 12 video ln SMPTE YCbCr 4:2:2 output pixels 3 10 VIDEO tpg type video y All 720p, 1080p and 1080i video formats supported (SMPTE TEST 296M and SMPTE 274M) 10 PATTERN video c GENERATOR Colour-bar output with choice off 8 different patterns video val All signals synchronous with the pixel clock clk Compatible with a wide range of video encoder ICs Tiny implementation size makes the core suitable for even the hd mode smallest FPGAs and CPLDs (0, 1 or 2) Applications Figure 1: SMPTE Test pattern generator Digital video testing and prototyping General Description Default output displays and simple screen savers The HD SMPTE TPG IP Core (Figure 1) is a versatile test pattern generator capable of producing a range of test patterns in 20-bit 4:2:2 Generic Parameters format. The output stream format is compliant with the SMPTE standards 296M and 274M. The module is ideal for use in the prototyping stages of digital video systems or as a known good reference source for standard Generic name Description Type Valid range 720p, 1080p or 1080i video. hd mode Output video mode integer 0: 720p The video mode is controlled by the generic parameter hd mode and the 1: 1080p video test pattern can be set using the parameter tpg type. In total there 2: 1080i are 8 different test patterns to choose from. The output video is a standard SMPTE 20-bit stream that is synchronous Pin-out Description with the clk signal. The clock frequency should be set to the value that corresponds to the correct pixel clock frequency for the corresponding video mode. For instance, the clock frequency should be set to 74.25 MHz for 720p60, 1080p30 or 1080i60 modes. A clock frequency of 148.5 Pin name I/O Description Active state MHz should be chosen for 1080p60. clk in Pixel clock rising edge (e.g. 148.5 MHz or 74.25 MHz depending on the Test pattern type required video stndard) reset in Asynchronous reset low By modifying the test pattern type, the colour and appearance of the test tpg type 2:0 in 000 : bars data pattern may be controlled. Figure 2 on the following page gives a 1 001 : blues description of each pattern available . 010 : reds 011 : greens The test pattern type may be programmed in real-time during normal 100 : yellows operation. The images shown are for a single frame of a 720p60 video 101 : browns (SMPTE 296M). The video blanking regions are also shown. Note that 110 : purples the vertical blue lines are where the EAV and SAV codes are positioned 111 : greys in the video stream. video ln 11:0 out Output video line number data video y 9:0 out Y-channel video output data video c 7:0 out C-channel video output data video val out SMPTE output video high 1 Additional test patterns may be provided on request. Please contact stream valid Zipcores for more information. Copyright 2019 www.zipcores.com Download this IP Core Page 1 of 3HD SMPTE TPG High-Definition SMPTE Test Pattern Generator Rev. 1.1 Functional Timing An example output waveform is shown in Figure 3 below. The 20-bit Y/C output data is valid on the rising clock-edge of clk when video val is high. The video val signal is active high one clock cycle after system reset. The current active line number is provided by the video ln signal which is a value from 0 to N. So for example, a 720p format stream has 750 lines in total (including blanking). This means that the video line number will run from 0 to 749. Figure 3: Typical SMPTE 296M/274M output stream (Note: video val and Figure 2: Different test pattern types. An SMPTE 296M video ln signals not shown) (720p) output video stream is shown as an example Copyright 2019 www.zipcores.com Download this IP Core Page 2 of 3 tpg type = 111 tpg type = 110 tpg type = 101 tpg type = 100 tpg type = 011 tpg type = 010 tpg type = 001 tpg type = 000 clk video y 3FF 000 000 XYZ 040 040 040 040 040 040 3FF 000 000 XYZ Y0 Y1 Y2 Y3 Y4 Y5 Y6 YN 3FF video c 3FF 000 000 XYZ 200 200 200 200 200 200 3FF 000 000 XYZ CB0 CR0 CB2 CR2 CB4 CR4 CB6 CRN 3FF Blanking EAV code SAV code Active video line