AS4C256M16D3LB Revision History 4Gb AS4C256M16D3LB 96 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Apr. 2016 Rev 1.1 Add Industrial part datasheet Jan. 2017 Rev 1.2 Add 1866Mbps / 933 MHz speed option Feb.2019 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 54 - Rev.1.2 Feb. 2019AS4C256M16D3LB Specifications Features - Density : 4G bits - Double-data-rate architecture two data transfers per clock cycle - Organization : 32M words x 16 bits x 8 banks - Package : - The high-speed data transfer is realized by the 8 bits - 96-ball FBGA prefetch pipelined architecture - Lead-free (RoHS compliant) and Halogen-free - Bi-directional differential data strobe (DQS and DQS) is - Power supply : VDD, VDDQ = 1.35V (1.283V to 1.45V) transmitted/received with data for capturing data at the re- - Backward compatible to VDD, VDDQ = 1.5V 0.075V ceiver - Data rate : - DQS is edge-aligned with data for READs center-aligned - 1600Mbps with data for WRITEs - 1866Mbps - Differential clock inputs (CK and CK) - 2KB page size - DLL aligns DQ and DQS transitions with CK transitions - Row address: A0 to A14 - Commands entered on each positive CK edge data and - Column address: A0 to A9 data mask referenced to both edges of DQS - Eight internal banks for concurrent operation - Data mask (DM) for write data - Burst lengths (BL) : 8 and 4 with Burst Chop (BC) - Posted CAS by programmable additive latency for better - Burst type (BT) : command and data bus efficiency - Sequential (8, 4 with BC) - On-Die Termination (ODT) for better signal quality - Interleave (8, 4 with BC) - Synchronous ODT - CAS Latency (CL) : 5, 6, 7, 8, 9, 10, 11,13 - Dynamic ODT - CAS Write Latency (CWL) : 5, 6, 7, 8, 9 - Precharge : auto precharge option for each burst access - Asynchronous ODT - Driver strength : RZQ/7, RZQ/6 (RZQ = 240 ) - Multi Purpose Register (MPR) for pre-defined pattern read - Refresh : auto-refresh, self-refresh out - Refresh cycles : - Average refresh period - ZQ calibration for DQ drive and ODT 7.8 s at -40C Tc +85C - Programmable Partial Array Self-Refresh (PASR) 3.9 s at +85C < Tc +95C - RESET pin for Power-up sequence and reset function - Operating case temperature range - SRT range : Normal/extended - Commercial Tc = 0C to +95C - Programmable Output driver impedance control - Industrial Tc = -40C to +95C Table 1. Ordering Information Part Number Org Temperature MaxClock (MHz) Package AS4C256M16D3LB-12BCN 800 256Mx16 96-ball FBGA Commercial 0C to +95C AS4C256M16D3LB-12BIN 800 256Mx16 96-ball FBGA Industrial -40C to +95C AS4C256M16D3LB-10BCN 933 256Mx16 96-ball FBGA Commercial 0C to +95C AS4C256M16D3LB-10BIN 933 256Mx16 96-ball FBGA Industrial -40C to +95C Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency tRCD (ns ) tRP (ns ) DDR3L-1600 800MHz 11 13.75 13.75 DDR3L-1866 933MHz 1 3 13. 91 13. 91 Confidential - 2 of 54 - Rev.1.2 Feb. 2019