78Q2120C 10/100BASE-TX Transceiver DATA SHEET January 2009 DESCRIPTION FEATURES The 78Q2120C is a 10BASE-T/100BASE-TX Fast 10BASE-T/100BASE-TX IEEE-802.3 compliant Ethernet transceiver. It includes integrated MII, TX and RX functions requiring a dual 1:1 ENDECs, scrambler/descrambler, dual-speed clock isolation transformer interface to the line recovery, and full-featured auto-negotiation function. Integrated MII, 10BASE-T/100BASE-TX ENDEC, The transmitter includes an on-chip pulse-shaper and 100BASE-TX scrambler/descrambler, and full- a low-power line driver. The receiver has an adaptive featured auto-negotiation function equalizer and a baseline restoration circuit required for accurate clock and data recovery. The transceiver Full duplex operation capable interfaces to Category-5 unshielded twisted pair (Cat- 5 UTP) cabling for 100BASE-TX/10BASE-T and PCS Bypass supports 5-bit symbol interface Category-3 unshielded twisted pair for 10BASE-T. Register-programmable transmit amplitude Connection to the line media is via 1:1 isolation transformers. No external filter is required. Interface Dual speed digital clock recovery to the MAC is accomplished through an IEEE-802.3 Automatic polarity correction during auto- compliant Media Independent Interface (MII). The negotiation and 10BASE-T signal reception product is fabricated in an advanced CMOS process for high performance and low power operation. Power-saving and power-down modes including transmitter disable LED indicators: LINK, TX, RX, COL, 100, 10, FDX User programmable Interrupt pin 64-Pin TQFP (JEDEC LQFP) package Single 3.3 V 0.3V Supply BLOCK DIAGRAM 44BB//55BB En Enccoderoder,, Pulse Shaper 100M100M NNRRZZ//NRZNRZII Pulse Shaper ScScrraammbblerler,, MLMLTT33 Enc Encooderder and Fiand Filtlterer PPaararalllleell//SSeeririaall TXOP/N RX CLK TXTX CL CLKK GE GENN MMII II MDMDII TX CLK 10M10M ReRegisgisttererss PaParraalllleell//SSeerriaial,l, RXIP/N & & MManchestanchesteer Er Ennccooddeerr RXD 3:0 InInteterrffaaccee AAututoo LogLogiicc NNegotegotiatiatiioonn TXD 3:0 CaCarrrrierier Sen Sensse,e, Collision Detect Collision Detect MaMancnchheesstteer r DDeeccoodeder,r, 10M10M 10100M0M PPaararallllel/Serel/Seriiaall CLK CLK AAdadaptptiivvee EQ, EQ, ReReccooveveryry BBaasseelliinene W Waannddeerr CoCorrrrecectt,, SerSeriialal//PParaaralllel lel MMLLTT33 D Deecode,code, NRNRZZII/NR/NRZZ DeDessccrraammbblleerr,, 5B/5B/44BB D Deeccooderder Clock Reference Clock Reference LELEDsDs PSPS LEDL LEDBTX LEDTX LEDCOL VCVCCC GNGNDD CKIN 25M25MHHzz LEDBT LEDFX LEDRX Page: 1 of 35 2009 Teridian Semiconductor Corporation Rev 1.3 78Q2120C 10/100BASE-TX Transceiver mode of operation, a 25MHz crystal should be FUNCTIONAL DESCRIPTION connected between the XTLP and XTLN pins. GENERAL Alternatively, an external 25MHz clock signal can be connected to the CKIN pin. The chip senses activity Power Management on the CKIN pin, and will automatically configure itself to use the external clock. In this mode of operation, a The 78Q2120C has three power saving modes: crystal is not required and the XTLP and XTLN pins should be left floating or connected together. Chip Power-Down Receive Power Management Transmit Clock Generation Transmit High Impedance Mode The transmitter uses an on-chip frequency Chip power-down is activated by setting the PWRDN synthesizer to generate the transmit clock. In bit in MII register MR0.11 or pulling high the PWRDN 100BASE-TX operation, the synthesizer multiplies the pin. When the chip is in the power-down mode, all reference clock by 5 to obtain the internal 125MHz on-chip circuitry is shut off, and the device serial transmit clock. In 10BASE-T mode, it consumes minimum power. While in the power- generates an internal 20MHz transmit clock by down state, the 78Q2120C still responds to multiplying the 25MHz reference clock by 4/5. The management transactions. synthesizer references either the local 25 MHz crystal oscillator, or the externally applied clock, depending Receive power management (RXCC mode) is on the selected mode of operation. activated by setting the RXCC bit in MII register MR16.0. In this mode of operation, the adaptive Receive Signal Qualification equalizer, the clock recovery phase lock loop (PLL), The integrated signal qualifier has separate squelch and all other receive circuitry will be powered down and unsquelch thresholds. It also includes a built-in when no valid MLT-3 signal is present at the UTP timer to ensure fast and accurate signal detection and receive line interface. As soon as a valid signal is line noise rejection. Upon detection of two or more detected, all circuits will automatically be powered valid 10BASE-T or 100BASE-TX pulses on the line up to resume normal operation. During this mode of receive port, signal detect is indicated. The signal operation, RX CLK will be inactive when there is no detect threshold is then lowered by about 40%. All data being received. Note that the RXCC mode is adaptive circuits are released from their initial states not supported during 10BASE-T operation. and allowed to lock onto the incoming data. In Transmit high impedance mode is activated by 100BASE-TX operation, signal detect is de-asserted setting the TXHIM bit in MII register MR16.12. In this when no signal is presented for a period of about mode of operation, the transmit UTP drivers are in a 1.2us. In 10BASE-T operation, signal detect is de- high impedance state and TX CLK is tri-stated. A asserted whenever no Manchester data is received. In weak internal pull-up is enabled on TX CLK. The either case, the signal detect threshold will return to the receive circuitry remains fully operational. The squelched level whenever the signal detect indication default state of MR16.12 is a logic low for disabling is de-asserted. Signal detect is also used to control the the transmit high impedance mode. The transmitter operation of the clock/data recovery circuit to assure is fully functional when MR16.12 is cleared. fast acquisition. Analog Biasing and Supply Regulation Receive Clock Recovery The 78Q2120C requires no external component to In 100BASE-TX mode, the 125MHz receive clock is generate on-chip bias voltages and currents. High extracted using a digital DLL-based loop. When no accuracy is maintained through a closed-loop receive signal is present, the CDR is directed to lock trimmed biasing network. onto the 125MHz transmit serial clock. When signal detect is asserted, the CDR will use the received MLT- On-chip digital logic runs off an internal voltage 3 signal as the clock reference. The recovered clock is regulator. Hence only a single Vcc supply is used to re-time the data signal and for conversion of required to power-up the device. The on-chip the data to NRZ format. regulator is not affected by the power-down mode. In 10BASE-T mode, the 10MHz receive clock is Clock Selection recovered digitally from the Manchester data using a DLL locked to the reference clock. When The 78Q2120C will use the on-chip crystal oscillator Manchester-coded preambles are detected, the as the clock source if the CKIN pin is tied low. In this Page: 2 of 35 2009 Teridian Semiconductor Corporation Rev 1.3