600 MHz, 32 16 Buffered Analog Crosspoint Switch Data Sheet AD8104/AD8105 FEATURES FUNCTIONAL BLOCK DIAGRAM D0 D1 D2 D3 D4 D5 VDD DGND High channel count, 32 16 high speed, nonblocking switch array AD8104/ A0 AD8105 A1 Differential or single-ended operation A2 Differential G = +1 (AD8104) or G = +2 (AD8105) A3 SER/PAR Pin compatible with AD8117/AD8118, 32 32 switch arrays WE 1 Flexible power supplies 192-BIT SHIFT REGISTER DATA 0 WITH 6-BIT CLK OUT PARALLEL LOADING Single +5 V supply, or dual 2.5 V supplies DATA IN Serial or parallel programming of switch array 96 96 High impedance output disable allows connection of UPDATE NO PARALLEL LATCH CONNECT multiple devices with minimal loading on output bus RESET 96 Excellent video performance >50 MHz 0.1 dB gain flatness DECODE 16 16 6:32 DECODERS 0.05% differential gain error (R = 150 ) L INPUT 512 0.05 phase error (R = 150 ) L OUTPUT RECEIVER BUFFER G = +1* Excellent ac performance G = +1 G = +2** 2 2 Bandwidth: 600 MHz Slew rate: 1800 V/s Settling time: 2.5 ns to 1% Low power of 1.7 W Low all hostile crosstalk SWITCH MATRIX < 70 dB at 5 MHz < 40 dB at 600 MHz Reset pin allows disabling of all outputs (connected through a capacitor to ground provides power-on reset capability) 304-ball BGA package (31 mm 31 mm) APPLICATIONS *AD8104 ONLY VPOS VNEG VOCM **AD8105 ONLY Routing of high speed signals including Figure 1. RGB and component video routing KVM Compressed video (MPEG, wavelet) Data communications while the AD8105 has a differential gain of +2 for ease of use GENERAL DESCRIPTION in back-terminated load applications. They operate as fully The AD8104/AD8105 are high speed, 32 16 analog crosspoint differential devices or can be configured for single-ended switch matrices. They offer 600 MHz bandwidth and slew rate of operation. Either a single +5 V supply or dual 2.5 V supplies 1800 V/s for high resolution computer graphics (RGB) signal can be used, while consuming only 340 mA of idle current with switching. With less than 70 dB of crosstalk and 90 dB isola- all outputs enabled. The channel switching is performed via a tion (at 5 MHz), the AD8104/AD8105 are useful in many high double-buffered, serial digital control (which can accommodate speed applications. The 0.1 dB flatness, which is greater than daisy-chaining of several devices), or via a parallel control, 50 MHz, makes the AD8104/AD8105 ideal for composite video allowing updating of an individual output without reprogram- switching. ming the entire array. The AD8104/AD8105 include 16 independent output buffers The AD8104/AD8105 are packaged in a 304-ball BGA package that can be placed into a high impedance state for paralleling and are available over the extended industrial temperature crosspoint outputs so that off-channels present minimal loading range of 40C to +85C. to an output bus. The AD8104 has a differential gain of +1, Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20072016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 32 INPUT PAIRS ENABLE/DISABLE SET INDIVIDUAL, OR RESET ALL OUTPUTS TO OFF 16 OUTPUT PAIRS 06612-001AD8104/AD8105 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................7 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions ..............................8 Functional Block Diagram .............................................................. 1 Truth Table and Logic Diagram ............................................... 13 General Description ......................................................................... 1 I/O Schematics ................................................................................ 15 Revision History ............................................................................... 2 Typical Performance Characteristics ........................................... 17 Specifications ..................................................................................... 3 Theory of Operation ...................................................................... 25 Timing Characteristics (Serial Mode) ....................................... 5 Applications Information .............................................................. 26 Timing Characteristics (Parallel Mode) .................................... 6 Programming .............................................................................. 26 Absolute Maximum Ratings ............................................................ 7 Operating Modes ........................................................................ 27 Thermal Resistance ...................................................................... 7 Outline Dimensions ....................................................................... 36 Power Dissipation ......................................................................... 7 Ordering Guide .......................................................................... 36 REVISION HISTORY 4/16Rev. 0 to Rev. A Changes to Off Isolation, Input to Output Parameter, Table 1 ........ 3 Change to Areas of Crosstalk Section .......................................... 32 Deleted Figure 73 Renumbered Sequentially ........................... 35 Changes to Ordering Guide .......................................................... 36 6/07Revision 0: Initial Version Rev. A Page 2 of 36