260 MHz, 16 5 Buffered Video Crosspoint Switches Data Sheet AD8106/AD8107 FEATURES FUNCTIONAL BLOCK DIAGRAM D0 D1 D2 D3 D4 16 5 high speed, nonblocking switch arrays AD8106: G = 1 A0 AD8107: G = 2 A1 CLK A2 Pin compatible with AD8110/AD8111, 16 8 switch arrays For a 16 16 array, see AD8114/AD8115 25-BIT REGISTER (RANK 1) For a 16 x 8 array, see AD8110/AD8111 Complete solution UPDATE 25 Buffered inputs PARALLEL LATCH SET INDIVIDUAL CE (RANK 2) OR RESET ALL Five output amplifiers OUTPUTS RESET 25 TO OFF Drives 150 loads 5 DECODE Excellent video performance 5 5:16 DECODERS 60 MHz 0.1 dB gain flatness OUTPUT AD8106/AD8107 BUFFER 0.02% differential gain error (R = 150 ) L 80 G = 1, G = 2 0.02 differential phase error (R = 150 ) L Excellent ac performance 3 dB bandwidth > 260 MHz 500 V/s slew rate SWITCH Low power of 50 mA MATRIX Low all-hostile crosstalk of 78 dB at 5 MHz 16 INPUTS 5 OUTPUTS Output disable allows connection of multiple device outputs Reset pin allows disabling of all outputs Excellent ESD rating: exceeds 4000 V human body model 80-lead LQFP (12 mm 12 mm) APPLICATIONS Figure 1. Routing of high speed signals including: Composite video (NTSC, PAL, S, SECAM) Component video (YUV, RGB) Compressed video (MPEG, Wavelet) 3-level digital video (HDB3) GENERAL DESCRIPTION The AD8106 and AD8107 are high speed, 16 5 video crosspoint The AD8106 and AD8107 include five independent output switch matrices. They offer a 3 dB signal bandwidth greater buffers that can be placed into a high impedance state for parallel- than 260 MHz, and channel switch times of less than 25 ns ing crosspoint outputs, preventing off channels from loading the with 1% settling. With 78 dB of crosstalk and 97 dB isolation output bus. The AD8106 has a gain of 1, while the AD8107 (at 5 MHz), the AD8106/AD8107 are useful in many high speed offers a gain of 2. Both operate on voltage supplies of 5 V while applications. The differential gain and differential phase of consuming only 30 mA of idle current. The channel switching is greater than 0.02% and 0.02 respectively, along with 0.1 dB performed via a parallel control, allowing updating of an individual flatness out to 60 MHz, make the AD8106/AD8107 ideal for output without reprogramming the entire array. video signal switching. The AD8106/AD8107 are offered in an 80-lead LQFP and are available over the extended industrial temperature range of 40C to +85C. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20062016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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ENABLE/DISABLE 05774-001AD8106/AD8107 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ........................................... 10 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 16 Functional Block Diagram .............................................................. 1 Power-On Reset .......................................................................... 16 General Description ......................................................................... 1 Initialization ................................................................................ 16 Revision History ............................................................................... 2 Gain Selection ............................................................................. 16 Specifications ..................................................................................... 3 Creating Larger Crosspoint Arrays .......................................... 16 Timing Characteristics ................................................................ 5 Crosstalk ...................................................................................... 18 Absolute Maximum Ratings ............................................................ 6 PCB Layout ................................................................................. 20 Maximum Power Dissipation ..................................................... 6 Outline Dimensions ....................................................................... 21 ESD Caution .................................................................................. 6 Ordering Guide .......................................................................... 21 Pin Configuration and Function Descriptions ............................. 8 Input/Output Schematics ................................................................ 9 REVISION HISTORY 5/16Rev. 0 to Rev. A Changes to Crosstalk, All Hostile Parameter and Off Isolation, Input/Output Parameter .................................................................. 3 Changes to Areas of Crosstalk Section ........................................ 18 Deleted Evaluation Board Section and Figure 48 Renumbered Sequentially .............................................................. 21 Moved Outline Dimensions and Ordering Guide ..................... 21 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 21 Deleted Figure 49 ............................................................................ 22 Deleted Figure 50 to Figure 52 ...................................................... 23 Deleted Figure 53 and Figure 54 ................................................... 24 Deleted Controlling the Evaluation Board from a PC Section, Figure 55, and Data-Line Overshoot on Printer Ports Section .................................................................................... 25 Deleted Figure 56 ............................................................................ 26 3/06Revision 0: Initial Version Rev. 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