325 MHz, 8 8 Buffered Video Crosspoint Switches Data Sheet AD8108/AD8109 FEATURES FUNCTIONAL BLOCK DIAGRAM SER/PAR 8 8 high speed nonblocking switch arrays D0 D1 D2 D3 AD8108: G = 1 A0 AD8109: G = 2 A1 CLK Serial or parallel programming of switch array A2 Serial data out allows daisy-chaining of multiple 8 8 arrays 32-BIT SHIFT REGISTER WITH 4-BIT DATA to create larger switch arrays DATA IN PARALLEL LOADING OUT Output disable allows connection of multiple devices UPDATE 32 Pin-compatible with AD8110/AD8111 16 8 switch arrays SET INDIVIDUAL CE PARALLEL LATCH OR RESET ALL For 16 16 arrays see AD8116 OUTPUTS RESET 32 TOOF Complete solution 8 DECODE Buffered inputs 8 4:8 DECODERS Eight output amplifiers OUTPUT AD8108 (G = 1) AD8108/AD8109 BUFFER 64 G = +1 AD8109 (G = 2) G = +2 Drives 150 loads Excellent video performance 60 MHz 0.1 dB gain flatness 0.02%/0.02 differential gain/differential phase error SWITCH MATRIX (R = 150 ) L 8 OUTPUTS 8 INPUTS Excellent ac performance 3 dB bandwidth: 325 MHz (AD8108), 250 MHz (AD8109) Slew rate: 400 V/s (AD8108), 480 V/s (AD8109) Low power of 45 mA Low all hostile crosstalk of 83 dB at 5 MHz Reset pin allows disabling of all outputs (connected through Figure 1. Functional Block Diagram a capacitor to ground provides power-on reset capability) Excellent ESD rating: exceeds 4000 V human body model and 0.02, respectively, along with 0.1 dB flatness out to 60 MHz, 80-lead LQFP (12 mm 12 mm) make the AD8108/AD8109 ideal for video signal switching. APPLICATIONS The AD8108 and AD8109 include eight independent output buffers that can be placed into a high impedance state for paral- Routing of high speed signals including leling crosspoint outputs so that off channels do not load the Composite video (NTSC, PAL, S, SECAM) output bus. The AD8108 has a gain of 1, while the AD8109 Component video (YUV, RGB) offers a gain of 2. They operate on voltage supplies of 5 V Compressed video (MPEG, Wavelet) while consuming only 45 mA of idle current. The channel 3-level digital video (HDB3) switching is performed via a serial digital control (which can GENERAL DESCRIPTION accommodate daisy-chaining of several devices) or via a parallel control allowing updating of an individual output without The AD8108/AD8109 are high speed 8 8 video crosspoint reprogramming the entire array. switch matrices. They offer a 3 dB signal bandwidth greater than 250 MHz and channel switch times of less than 25 ns with 1% The AD8108/AD8109 is packaged in an 80-lead LQFP and is settling. With 83 dB of crosstalk and 98 dB isolation (at 5 MHz), available over the extended industrial temperature range of the AD8108/AD8109 are useful in many high speed applications. 40C to +85C. The differential gain and differential phase of better than 0.02% Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 19972016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. ENABLE/DISABLE 01068-001AD8108/AD8109 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Input/Output Schematics .............................................................. 17 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 18 General Description ......................................................................... 1 Applications ................................................................................ 18 Functional Block Diagram .............................................................. 1 Power-On RESET ....................................................................... 19 Revision History ............................................................................... 2 Gain Selection ............................................................................. 19 AD8108/AD8109Specifications .................................................. 3 Creating Larger Crosspoint Arrays .......................................... 20 Timing Characteristics (Serial) .................................................. 5 Multichannel Video ................................................................... 21 Timing Characteristics (Parallel) ............................................... 6 Crosstalk ...................................................................................... 22 Absolute Maximum Ratings ............................................................ 8 PCB Layout ...................................................................................... 24 Maximum Power Dissipation ..................................................... 8 Outline Dimensions ....................................................................... 25 ESD Caution .................................................................................. 8 Ordering Guide .......................................................................... 25 Pin Configuration and Function Descriptions ............................. 9 Typical Performance Characteristics ........................................... 11 REVISION HISTORY 5/2016Rev. B to Rev. C 9/2005Rev. A to Rev. B Changes to Crosstalk, All Hostile Parameter and Off Isolation, Updated Format .................................................................. Universal Input-Output Parameter, Table 3 .................................................... 3 Change to Absolute Maximum Ratings ......................................... 8 Changes to Areas of Crosstalk Section ........................................ 22 Changes to Maximum Power Dissipation Section ........................ 8 Change to Figure 4 ............................................................................ 8 Changes to PCB Layout Section ................................................... 24 Deleted Figure 52 Renumbered Sequentially ............................ 24 Updated Outline Dimensions ....................................................... 30 Deleted Figure 53 and Figure 54 ................................................... 25 Changes to Ordering Guide .......................................................... 30 Moved Outline Dimensions and Ordering Guide ..................... 25 Updated Outline Dimensions ....................................................... 25 1/2002Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 25 Changed MQFP to LQFP .................................................. Universal Deleted Figure 55 and Figure 56 ................................................... 26 Updated Outline Dimensions ....................................................... 27 Deleted Figure 57 ............................................................................ 27 Deleted Evaluation Board Section, Control the Evaluation 10/1997Revision 0: Initial Version Board from a PC Section, Figure 58, Overshoot of PC Printer Ports Data Lines Section, and Figure 59 ..................................... 28 Deleted Figure 60 ............................................................................ 29 Rev. C Page 2 of 27