600 MHz, 32 32 Buffered, Analog Crosspoint Switch Data Sheet AD8117/AD8118 FEATURES FUNCTIONAL BLOCK DIAGRAM D0 D1 D2 D3 D4 D5 VDD DGND High channel count, 32 32 high speed, nonblocking switch AD8117/ A0 array AD8118 A1 Differential or single-ended operation A2 A3 Differential G = +1 (AD8117) or G = +2 (AD8118) SER/PAR A4 Flexible power supplies WE 1 192-BIT SHIFT REGISTER Single +5 V supply, or dual 2.5 V supplies DATA 0 WITH 6-BIT CLK OUT PARALLEL LOADING Serial or parallel programming of switch array DATA IN High impedance output disable allows connection of 192 UPDATE multiple devices with minimal loading on output bus PARALLEL LATCH RESET Excellent video performance 192 >50 MHz 0.1 dB gain flatness DECODE 32 0.05%/0.05 differential gain/phase error (R = 150 ) L 32 6:32 DECODERS Excellent ac performance INPUT 1024 OUTPUT RECEIVER Bandwidth: 600 MHz BUFFER G = +1* G = +1 G = +2** Slew rate: 1800 V/s 2 2 Settling time: 2.5 ns to 1% Low power of 2.5 W Low all hostile crosstalk < 70 dB at 5 MHz SWITCH < 43 dB at 600 MHz MATRIX Reset pin allows disabling of all outputs (connected through a capacitor to ground provides power-on reset capability) 304-ball BGA package (31 mm 31 mm) APPLICATIONS Routing of high speed signals including RGB and component *AD8117 ONLY video routing VPOS VNEG VOCM **AD8118 ONLY KVM Figure 1. Compressed video (MPEG, wavelet) Data communications GENERAL DESCRIPTION The AD8117/AD8118 are high speed, 32 32 analog crosspoint back terminated load applications. They operate as fully switch matrices. They offer 600 MHz bandwidth and slew rate of differential devices or can be configured for single-ended 1800 V/s for high resolution computer graphics (RGB) signal operation. Either a single +5 V supply or dual 2.5 V supplies switching. With less than 70 dB of crosstalk and 80 dB can be used, while consuming only 500 mA of idle current with isolation (at 5 MHz), the AD8117/AD8118 are useful in many all outputs enabled. The channel switching is performed via a high speed applications. The 0.1 dB flatness greater than double-buffered, serial digital control (which can accommodate 50 MHz makes the AD8117/AD8118 ideal for composite video daisy chaining of several devices), or via a parallel control, allowing updating of an individual output without reprogram- switching. ming the entire array. The AD8117/AD8118 include 32 independent output buffers that can be placed into a high impedance state for paralleling The AD8117/AD8118 are packaged in a 304-ball BGA package crosspoint outputs so that off-channels present minimal loading and are available over the extended industrial temperature to an output bus. The AD8117 has a differential gain of +1, range of 40C to +85C. while the AD8118 has a differential gain of +2 for ease of use in Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20072016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. OBSOLETE 32 INPUT PAIRS ENABLE/DISABLE SET INDIVIDUAL, OR RESET ALL OUTPUTS TO OFF 32 OUTPUT PAIRS 06365-001AD8117/AD8118 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................7 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions ..............................8 Functional Block Diagram .............................................................. 1 Truth Table and Logic Diagram ............................................... 13 General Description ......................................................................... 1 Input/Output Schematics .............................................................. 15 Revision History ............................................................................... 2 Typical Performance Characteristics ........................................... 17 Specifications ..................................................................................... 3 Theory of Operation ...................................................................... 25 Timing Characteristics (Serial Mode) ....................................... 5 Applications Information .............................................................. 26 Timing Characteristics (Parallel Mode) .................................... 6 Programming .............................................................................. 26 Absolute Maximum Ratings ............................................................ 7 Operating Modes ........................................................................ 27 Thermal Resistance ...................................................................... 7 Outline Dimensions ....................................................................... 36 Power Dissipation ......................................................................... 7 Ordering Guide .......................................................................... 36 REVISION HISTORY 5/16Rev. A to Rev. B Changes to General Description Section ...................................... 1 Changes to Off Isolation, Input-Output Parameter, Table 1 ....... 3 5/07Rev. 0 to Rev. A Added AD8118 ................................................................... Universal Changes to Data Sheet Title ........................................................... 1 Changes to Table 1 ............................................................................ 3 2/07Revision 0: Initial Version Rev. B Page 2 of 36 OBSOLETE