34 34, 3.2 Gbps Asynchronous Digital Crosspoint Switch Data Sheet AD8152 FEATURES FUNCTIONAL BLOCK DIAGRAM VCC Low cost Low power: 2.5 V (outputs disabled) 34 34 IN33P TO OUT33P TO 34 34, fully differential, nonblocking array IN00P OUT00P 34 34 OUTPUT DIFFERENTIAL 3.2 Gbps per port NRZ data rate VTTI LEVEL VTTO SWITCH MATRIX DACs 34 34 Wide power supply range: 2.5 V to 3.3 V IN33N TO OUT33N TO IN00N OUT00N LVTTL or LVCMOS level control inputs at 2.5 V to 3.3 V MATRIX Low channel jitter: 45 ps p-p CONNECTION D0 TO D5 CONNECTION DECODE LATCHES Drives a backplane directly OUTPUT LEVEL Programmable output swing LATCHES RESET 100 mV to 1600 mV p-p differential CS 50 on-chip input/output termination A0 TO A6 CONTROL User controlled voltage at the load LOGIC RE Minimizes power dissipation WE AD8152 Dual rank latches UPDATE Available in 256-ball BGA ED package VEE APPLICATIONS Figure 1. Fiber optic network switching High speed serial backplane routing to OC-48 with FEC Gigabit ethernet Digital video (HDTV) Data storage networks GENERAL DESCRIPTION The AD8152 is a breakthrough cross point switch offering a The fully differential signal path of the AD8152 reduces jitter large switch array (34 34) on very little power, typically 2.0 W. and crosstalk and allows the use of smaller single-ended voltage Additionally, the device operates at data rates up to 3.2 Gbps per swings. The device is offered in a 256-ball BGA ED package port, making it suitable for Sonet/SDH OC-48 with forward that operates over the industrial temperature range of 0C to error correction (FEC). 85C. The useful supply voltage range of the AD8152 allows the user to operate at LVPECL/CML data levels down to 2.5 V. The control interface is low voltage transistor transistor logic (LVTTL) or low voltage complementary metal-oxide (LVCMOS) compatible on 2.5 V to 3.3 V. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20022019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 02984-001AD8152 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions ..............................9 Applications ....................................................................................... 1 Typical Performance Characteristics ........................................... 14 General Description ......................................................................... 1 Test Circuits ..................................................................................... 18 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 19 Revision History ............................................................................... 2 Control Pin Description ............................................................ 19 Specifications ..................................................................................... 3 AD8152 Power Consumption .................................................. 22 Timing Specifications .................................................................. 4 Outputs ........................................................................................ 24 Absolute Maximum Ratings ............................................................ 8 Outline Dimensions ....................................................................... 25 Maximum Power Dissipation ..................................................... 8 Ordering Guide .......................................................................... 25 Thermal Resistance ...................................................................... 8 ESD Caution .................................................................................. 8 REVISION HISTORY 9/2019Rev. A to Rev. B Changes to Output Addressing Section, Connection and Output Updated Format .................................................................. Universal Current Programming Section, Using the Data Bus Section, and Removed Xstream ......................................................... Throughout Register Control Signals Section .................................................. 20 Deleted Figure 2 Renumbered Sequentially ................................. 1 Deleted Evaluation Board and PCB Layout Hints Section, Changes to Features Section, General Description, and Figure 1.... 1 Figure 10, and Figure 11 ................................................................ 21 Deleted Thermal Characteristics Parameters, Table 1 ................. 2 Changed Input/Output Coupling Section to Internal Changed Electrical Characteristics Section to Specifications Input/Output Termination Section .............................................. 21 Section ................................................................................................ 3 Changes to Internal Input/Output Termination Section, Input Added Timing Specifications Section, Table 3 Renumbered Coupling Section, and Output Coupling Section ...................... 21 Sequentially, and Endnote 1, Table 4.............................................. 4 Deleted Figure 12 to Figure 14, Board Construction or Stack-Up Moved Table 2 and Table 4 to Table 6 ............................................... 4 Section, and Bypass Capacitor Layout Section ........................... 22 Changes to Timing Specifications Section, Table 2, Table 4, and Changes to AD8152 Power Consumption Section .................... 22 Table 5 ................................................................................................ 4 Deleted Figure 15, Figure 16, and Connections for Testing Moved Table 7 to Table 11 ............................................................... 5 Section .............................................................................................. 23 Changes to Input Termination Resistors Section and Input Stage Added Endnote 1 to Table 10 .......................................................... 5 Changes to Endnote 1, Table 9, and Table 7 to Table 11 ............. 5 Section .............................................................................................. 23 Added Timing Diagrams Section ................................................... 6 Deleted Evaluation Board Control Software Section and Moved Figure 2 to Figure 4 ............................................................. 6 Figure 14 .......................................................................................... 24 Moved Figure 5 and Figure 6 .......................................................... 7 Changes to Power Saving Consideration Section .......................... 24 Added Thermal Resistance Section and Table 13 ........................ 8 Deleted Figure 18 ............................................................................ 25 Changes to Table 12 and Figure 7 ................................................... 8 Moved Ordering Guide Section ...................................................... 25 Changes to Figure 8 .......................................................................... 9 Updated Outline Dimensions ....................................................... 25 Changes to Table 14 ........................................................................ 10 Changes to Ordering Guide .......................................................... 25 Changes to Figure 16 and Figure 18 ............................................. 15 Deleted Figure 19 ............................................................................ 26 Changes to Figure 21 Caption, Figure 22, Figure 23 Caption, Deleted Figure 20 ............................................................................ 27 Figure 25 Caption, and Figure 26 ................................................. 16 Deleted Figure 21 ............................................................................ 28 Added Test Circuits Section .......................................................... 18 Deleted Figure 22 ............................................................................ 29 Changes to Figure 31 to Figure 33 ................................................ 18 Deleted Figure 23 ............................................................................ 30 Changed Control Interface Section to Theory of Operation Section, A 6:0 Inputs Section to A0 to A6 Inputs Section, 1/2003Rev. 0 to Rev. A D 5:0 Inputs Section to D5 to D0 Inputs Section ..................... 19 Edits to Specifications ....................................................................... 2 9/2002Revision 0: Initial Version Rev. B Page 2 of 25