6.5 Gbps Dual Buffer Mux/Demux AD8155 FEATURES FUNCTIONAL BLOCK DIAGRAM Dual 2:1 mux/1:2 demux RECEIVE TRANSMIT Optimized for dc to 6.5 Gbps NRZ data EQUALIZATION PRE- Per-lane P/N pair inversion for routing ease EMPHASIS Ix A 1:0 EQ Programmable input equalization 2:1 Compensates up to 40 inches of FR4 Ox C 1:0 Loss-of-signal detection Ix B 1:0 EQ Programmable output preemphasis up to 12 dB Programmable output levels with squelch and disable Ox A 1:0 Accepts ac-coupled or dc-coupled differential CML inputs 1:2 EQ Ix C 1:0 50 on-chip termination Ox B 1:0 1:2 demux supports unicast or bicast operation DUAL Port-level loopback 2:1 TRANSMIT RECEIVE Port or single lane switching MULTIPLEXER/ PRE- EQUALIZATION 1:2 1.8 V to 3.3 V flexible core supply EMPHASIS DEMULTIPLEXER User-settable I/O supply from V to 1.2 V CC Low power, typically 2.0 W in basic configuration LB A LB B 64-lead LFCSP 2 LB C SCL I C CONTROL PE A 40C to +85C operating temperature range SDA LOGIC I2C A 2:0 PE B PE C APPLICATIONS CONTROL EQ A LOGIC EQ B Low cost redundancy switch EQ C SEL 1:0 SONET OC48/SDH16 and lower data rates BICAST RXAUI, 4 Fibre Channel, Infiniband, and GbE over SEL4G AD8155 RESET backplane LOS INT OIF CEI 6.25 Gbps over backplane Serial data-level shift Figure 1. 2-/4-/6-lane equalizers or redrivers The main application of the AD8155 is to support redundancy GENERAL DESCRIPTION on both the backplane and the line interface sides of a serial The AD8155 is an asynchronous, protocol-agnostic, dual-lane link. The demultiplexing path implements unicast and bicast 2:1 switch with a total of six differential CML inputs and capability, allowing the part to support either 1 + 1 or 1:1 six differential CML outputs. The signal path supports NRZ redundancy. signaling with data rates up to 6.5 Gbps per lane. Each lane The AD8155 is also suited for testing high speed serial links offers programmable receive equalization, programmable because of its ability to duplicate incoming data. In a port- output preemphasis, programmable output levels, and loss-of- monitoring application, the AD8155 can maintain link signal detection. connectivity with a pass-through connection from Port C to The nonblocking switch core of the AD8155 implements a Port A while sending a duplicate copy of the data to test 2:1 multiplexer and 1:2 demultiplexer per lane and supports equipment on Port B. independent lane switching through the two select pins, The rich feature set of the AD8155 can be controlled either SEL 1:0 . Each port is a two-lane link. Every lane implements through external toggle pins or by setting on-chip control an asynchronous path supporting dc to 6.5 Gbps NRZ data, 2 registers through the I C interface. fully independent of other lanes. The AD8155 has low latency and very low lane-to-lane skew. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 08262-001AD8155 TABLE OF CONTENTS Features .............................................................................................. 1 AD8155 Power Consumption .................................................. 22 2 Applications ....................................................................................... 1 I C Control Interface ...................................................................... 24 Functional Block Diagram .............................................................. 1 Serial Interface General Functionality..................................... 24 2 General Description ......................................................................... 1 I C Interface Data Transfers: Data Write ................................ 24 2 Revision History ............................................................................... 2 I C Interface Data Transfers: Data Read ................................. 25 Specif icat ions ..................................................................................... 3 Applications Information .............................................................. 26 2 I C Timing Specifications ............................................................ 5 Output Compliance ................................................................... 27 Absolute Maximum Ratings ............................................................ 6 Signal Levels and Common-Mode Shift for AC-Coupled and DC-Coupled Outputs ................................................................ 28 ESD Caution .................................................................................. 6 Supply Sequencing ..................................................................... 30 Pin Configuration and Function Descriptions ............................. 7 Single Supply vs. Multiple Supply Operation ......................... 30 Typical Performance Characteristics ............................................. 9 Initialization Sequence for Low Power and LOS INT Theory of Operation ...................................................................... 15 Operation .................................................................................... 30 The Switch (Mux/Demux/Unicast/Bicast/Loopback) ........... 16 Printed Circuit Board (PCB) Layout Guidelines ................... 31 Receivers ...................................................................................... 18 Register Map ................................................................................... 33 Loss of Signal (LOS) ................................................................... 20 Outline Dimensions ....................................................................... 35 Transmitters ................................................................................ 21 Ordering Guide .......................................................................... 35 REVISION HISTORY 7/09Revision 0: Initial Version Rev. 0 Page 2 of 36