3.2 Gbps Quad Buffer Mux/Demux Data Sheet AD8159 FEATURES FUNCTIONAL BLOCK DIAGRAM Port level 2:1 mux/1:2 demux RECEIVE TRANSMIT I/O EQUALIZATION PRE- CROSS- Each port consists of 4 lanes EMPHASIS OVER SWITCH Ix A 3:0 EQ Each lane runs from dc to 3.2 Gbps, independent of the other Ox C 3:0 / 2:1 Ix C 3:0 lanes Ix B 3:0 EQ Compensates over 40 inches of FR4 at 3.2 Gbps through 2 levels of input equalization or 4 levels of output pre-emphasis Ox A 3:0 Accepts ac- or dc-coupled differential CML inputs 1:2 Ix C 3:0 / EQ Ox C 3:0 Low deterministic jitter, typically 20 ps p-p Ox B 3:0 Low random jitter, typically 1 ps rms TRANSMIT QUAD RECEIVE LB A 16 PRE- 2:1 EQUALIZATION BER < 10 LB B EMPHASIS MULTIPLEXER/ 1:2 LB C DEMULTIPLEXER PE A 1:0 On-chip termination PE B 1:0 PE C 1:0 Reversible inputs and outputs on one port CONTROL EQ A LOGIC EQ B Unicast or bicast on 1:2 demux function EQ C SEL 3:0 Port level loopback capability BICAST AD8159 REVERSE C Single lane switching capability 3.3 V core supply Figure 1. Flexible I/O supply down to 2.5 V Low power, typically 1 W in basic configuration 100-lead TQFP EP 40C to +85C operating temperature range APPLICATIONS Low cost redundancy switch SONET OC-48/SDH-16 and lower data rates XAUI (10 gigabit Ethernet) over backplane Gigabit Ethernet over backplane Fibre Channel 1.06 Gbps and 2.125 Gbps over backplane InfiniBand over backplane PCI Express (PCIe) over backplane GENERAL DESCRIPTION 1 The AD8159 is an asynchronous, protocol agnostic, quad-lane The main application of the AD8159 is to support redundancy 2:1 switch with 12 differential PECL-/CML-compatible inputs and on both the backplane side and the line interface side of a serial 12 differential CML outputs. The operation of this product is link. The device has unicast and bicast capability therefore, it optimized for NRZ signaling with data rates of up to 3.2 Gbps can be configured to support either 1 + 1 or 1:1 redundancy. per lane. Each lane offers two levels of input equalization and four The AD8159 supports reversing of the output and input pins levels of output pre-emphasis. on one of its ports, which helps to connect two ASICs with The AD8159 consists of four multiplexers and four demultiplexers, opposite pinouts. one per lane. Each port is a four-lane link, and each lane runs up to The AD8159 is also used for testing high speed serial links by a 3.2 Gbps data rate, independent of the other lanes. The lanes are duplicating incoming data and sending it to the destination port switched independently using the four select pins, SEL 3:0 each and to the test equipment simultaneously. select pin controls one lane of the port. The AD8159 has low latency and very low lane-to-lane skew. 1 Product covered by one or more patents: U.S. Patent No. 7,813,706. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20052018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 05611-001AD8159 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 15 Applications ....................................................................................... 1 Input Equalization (EQ) and Output Pre-Emphasis (PE) .... 15 General Description ......................................................................... 1 Loopback ..................................................................................... 16 Functional Block Diagram .............................................................. 1 Port C Reverse (Crossover) Capability .................................... 17 Revision History ............................................................................... 2 Applications Information .............................................................. 18 Specifications ..................................................................................... 3 Interfacing to the AD8159 ............................................................. 19 Absolute Maximum Ratings ............................................................ 4 Termination Structures .............................................................. 19 ESD Caution .................................................................................. 4 Input Compliance ....................................................................... 19 Pin Configuration and Function Descriptions ............................. 5 Output Compliance ................................................................... 20 Typical Performance Characteristics ............................................. 8 Outline Dimensions ....................................................................... 21 Evaluation Board Simplified Block Diagrams ............................ 13 Ordering Guide .......................................................................... 21 Test Circuits ..................................................................................... 14 REVISION HISTORY 10/2018Rev. B to Rev. C 4/2006Rev. 0 to Rev. A Added Patent Information .............................................................. 1 Changes to Applications Section ..................................................... 1 Changes to Table 5 .......................................................................... 15 5/2009Rev. A to Rev. B Updates to Outline Dimensions ................................................... 22 Changes to Input Voltage Swing Parameter, Table 1 .................... 3 Changes to Ordering Guide .......................................................... 22 Added VTTI, VTTO, VTTIO, VTTOI Parameter, Table 1 ....................... 3 Changes to Table 3 ............................................................................ 5 9/2005Revision 0: Initial Version Changes to Figure 24 ...................................................................... 11 Deleted Figure 30 Renumbered Sequentially ............................ 12 Deleted Figure 33 ............................................................................ 13 Changes to Figure 32 ...................................................................... 14 Changes to Table 5 and Table 6 ..................................................... 15 Deleted Table 7, Table 8, Table 10, and Table 11 ........................ 16 Changes to Applications Information Section ............................ 18 Changes to Termination Structures Section, Figure 39, Figure 40, and Figure 42 ................................................................ 19 Added Figure 41 Renumbered Sequentially .............................. 19 Deleted DC Coupling Section and Figure 44 ............................. 20 Changes to Output Compliance Section ..................................... 20 Added Figure 43, Table 9, Table 10, and Table 11 ...................... 20 Deleted AC Coupling Section, Output Compliance Table Section, and Table 13 ...................................................................... 21 Added Exposed Pad Notation to Outline Dimensions ............. 21 Changes to Ordering Guide .......................................................... 21 Rev. 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