RF Agile Transceiver Data Sheet AD9361 FEATURES FUNCTIONAL BLOCK DIAGRAM RX1B P, RF 2 2 transceiver with integrated 12-bit DACs and ADCs RX1B N AD9361 TX band: 47 MHz to 6.0 GHz RX1A P, ADC RX1A N RX band: 70 MHz to 6.0 GHz RX1C P, Supports TDD and FDD operation RX1C N RX2B P, Tunable channel bandwidth: <200 kHz to 56 MHz RX2B N Dual receivers: 6 differential or 12 single-ended inputs RX2A P, ADC RX2A N Superior receiver sensitivity with a noise figure of 2 dB at RX2C P, P0 D11:D0 / RX LO RX2C N 800 MHz LO TX D5:D0 RX gain control P1 D11:D0 / TX MON1 TX LO RX D5:D0 Real-time monitor and control signals for manual gain TX1A P, DAC TX1A N Independent automatic gain control TX1B P, TX1B N Dual transmitters: 4 differential outputs TX MON2 Highly linear broadband transmitter TX2A P, TX EVM: 40 dB DAC TX2A N TX noise: 157 dBm/Hz noise floor TX2B P, RADIO GPO TX2B N SWITCHING TX monitor: 66 dB dynamic range with 1 dB accuracy SPI Integrated fractional-N synthesizers CTRL PLLs CLK OUT CTRL 2.4 Hz maximum local oscillator (LO) step size AUXADC AUXDACx XTALP XTALN Multichip synchronization NOTES CMOS/LVDS digital interface 1. SPI, CTRL, P0 D11:D0 /TX D5:D0 , P1 D11:D0 /RX D5:D0 , AND RADIO SWITCHING CONTAIN MULTIPLE PINS. APPLICATIONS Figure 1. Point to point communication systems Femtocell/picocell/microcell base stations General-purpose radio systems impulse response (FIR) filters to produce a 12-bit output signal at GENERAL DESCRIPTION the appropriate sample rate. The AD9361 is a high performance, highly integrated radio frequency (RF) Agile Transceiver designed for use in 3G and The transmitters use a direct conversion architecture that achieves 4G base station applications. Its programmability and wideband high modulation accuracy with ultralow noise. This transmitter capability make it ideal for a broad range of transceiver applications. design produces a best in class TX error vector magnitude (EVM) The device combines a RF front end with a flexible mixed-signal of <40 dB, allowing significant system margin for the external baseband section and integrated frequency synthesizers, simplifying power amplifier (PA) selection. The on-board transmit (TX) design-in by providing a configurable digital interface to a power monitor can be used as a power detector, enabling highly processor. The AD9361 receiver LO operates from 70 MHz to accurate TX power measurements. 6.0 GHz and the transmitter LO operates from 47 MHz to 6.0 GHz The fully integrated phase-locked loops (PLLs) provide low range, covering most licensed and unlicensed bands. Channel power fractional-N frequency synthesis for all receive and bandwidths from less than 200 kHz to 56 MHz are supported. transmit channels. Channel isolation, demanded by frequency The two independent direct conversion receivers have state-of-the- division duplex (FDD) systems, is integrated into the design. art noise figure and linearity. Each receive (RX) subsystem includes All VCO and loop filter components are integrated. independent automatic gain control (AGC), dc offset correction, The core of the AD9361 can be powered directly from a 1.3 V quadrature correction, and digital filtering, thereby eliminating regulator. The IC is controlled via a standard 4-wire serial port the need for these functions in the digital baseband. The AD9361 and four real-time input/output control pins. Comprehensive also has flexible manual gain modes that can be externally power-down modes are included to minimize power consumption controlled. Two high dynamic range analog-to-digital converters during normal use. The AD9361 is packaged in a 10 mm 10 mm, (ADCs) per channel digitize the received I and Q signals and pass 144-ball chip scale package ball grid array (CSP BGA). them through configurable decimation filters and 128-tap finite Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20132016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. ADC DAC DAC DATA INTERFACE 10453-001AD9361 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 33 Applications ....................................................................................... 1 General......................................................................................... 33 Functional Block Diagram .............................................................. 1 Receiver........................................................................................ 33 General Description ......................................................................... 1 Transmitter .................................................................................. 33 Revision History ............................................................................... 2 Clock Input Options .................................................................. 33 Specifications ..................................................................................... 3 Synthesizers ................................................................................. 34 Current ConsumptionVDD Interface .................................. 8 Digital Data Interface................................................................. 34 Current ConsumptionVDDD1P3 DIG and VDDAx Enable State Machine ................................................................. 34 (Combination of all 1.3 V Supplies) ......................................... 10 SPI Interface ................................................................................ 35 Absolute Maximum Ratings ..................................................... 15 Control Pins ................................................................................ 35 Reflow Profile .............................................................................. 15 GPO Pins (GPO 3 to GPO 0) ................................................. 35 Thermal Resistance .................................................................... 15 Auxiliary Converters .................................................................. 35 ESD Caution ................................................................................ 15 Powering the AD9361 ................................................................ 35 Pin Configuration and Function Descriptions ........................... 16 Packaging and Ordering Information ......................................... 36 Typical Performance Characteristics ........................................... 20 Outline Dimensions ................................................................... 36 800 MHz Frequency Band ......................................................... 20 Ordering Guide .......................................................................... 36 2.4 GHz Frequency Band .......................................................... 25 5.5 GHz Frequency Band .......................................................... 29 REVISION HISTORY 11/2016Rev. E to Rev. F 11/2013Rev. C to Rev. D Changes to Features Section and General Description Section . 1 Changes to Ordering Guide .......................................................... 36 Change to TransmitterGeneral, Center Frequency Parameter, Minimum Column, Table 1 ............................................................. 4 9/2013Revision C: Initial Version 11/2014Rev. D to Rev. E Changes to Table 1 ............................................................................ 7 Rev. F Page 2 of 36