Integrated, Dual RF Transceiver with Observation Path Data Sheet AD9371 FEATURES FUNCTIONAL BLOCK DIAGRAM AD9371 Dual differential transmitters (Tx) RX1+ RX1 DECIMATION, Dual differential receivers (Rx) RX1 LPF RX2 pFIR, DC OFFSET Observation receiver (ORx) with 2 inputs RX2+ ADC QEC, TUNING, Sniffer receiver (SnRx) with 3 inputs RX2 LPF RSSI, OVERLOAD ADC Tunable range: 300 MHz to 6000 MHz MICRO- CONTROLLER Tx synthesis bandwidth (BW) to 250 MHz RX EXTLO+ LO RF GENERATOR SYNTHESIZER RX EXTLO Rx BW: 8 MHz to 100 MHz EXTERNAL OPTION Supports frequency division duplex (FDD) and time division TX1+ SPI TX1 PORT duplex (TDD) operation TX1 LPF TX2 DAC TX2+ Fully integrated independent fractional-N radio frequency (RF) pFIR, TX2 LPF synthesizers for Tx, Rx, ORx, and clock generation QEC, INTERPOLATION DAC JESD204B digital interface TX EXTLO+ LO RF APPLICATIONS GENERATOR SYNTHESIZER TX EXTLO EXTERNAL GPIO OPTION AUXADC 3G/4G micro and macro base stations (BTS) AUXDAC LO GENERATOR 3G/4G multicarrier picocells RF FDD and TDD active antenna systems SYNTHESIZER CLOCK Microwave, nonline of sight (NLOS) backhaul systems GENERATOR OBSERVATION Rx ORX1+ GENERAL DESCRIPTION ORX1 ORX2+ The AD9371 is a highly integrated, wideband RF transceiver ORX2 offering dual channel transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC SNIFFER SNRXA+ DECIMATION, Rx LPF pFIR, SNRXA delivers a versatile combination of high performance and low ADC AGC, SNRXB+ DC OFFSET, power consumption required by 3G/4G micro and macro BTS SNRXB LPF QEC, TUNING, SNRXC+ ADC RSSI, equipment in both FDD and TDD applications. The AD9371 SNRXC OVERLOAD operates from 300 MHz to 6000 MHz, covering most of the licensed and unlicensed cellular bands. The IC supports receiver NOTES 1. FOR JESD204B PINS, SEE FIGURE 4. bandwidths up to 100 MHz. It also supports observation receiver Figure 1. and transmit synthesis bandwidths up to 250 MHz to The high speed JESD204B interface supports lane rates up to accommodate digital correction algorithms. 6144 Mbps. Four lanes are dedicated to the transmitters and four The transceiver consists of wideband direct conversion signal lanes are dedicated to the receiver and observation receiver channels. paths with state-of-the-art noise figure and linearity. Each complete The fully integrated phase-locked loops (PLLs) provide high receiver and transmitter subsystem includes dc offset correction, performance, low power fractional-N frequency synthesis for quadrature error correction (QEC), and programmable digital the transmitter, the receiver, the observation receiver, and the filters, eliminating the need for these functions in the digital clock sections. Careful design and layout techniques provide the baseband. Several auxiliary functions such as an auxiliary analog- isolation demanded in high performance base station applications. to-digital converter (ADC), auxiliary digital-to-analog converters All voltage controlled oscillator (VCO) and loop filter components (DACs), and general-purpose input/outputs (GPIOs) are integrated are integrated to minimize the external component count. to provide additional monitoring and control capability. A 1.3 V supply is required to power the core of the AD9371, and An observation receiver channel with two inputs is included to a standard 4-wire serial port controls it. Other voltage supplies monitor each transmitter output and implement interference provide proper digital interface levels and optimize transmitter mitigation and calibration applications. This channel also connects and auxiliary converter performance. The AD9371 is packaged in a to three sniffer receiver inputs that can monitor radio activity in 12 mm 12 mm, 196-ball chip scale ball grid array (CSP BGA). different bands. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20162017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. JESD204B DEV CLK IN+, CTRL I/F JESD204B SPI JESD204B DEV CLK IN 14651-001AD9371 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 5.5 GHz Band .............................................................................. 46 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 54 General Description ......................................................................... 1 Transmitter (Tx) ......................................................................... 54 Functional Block Diagram .............................................................. 1 Receiver (Rx) ............................................................................... 54 Revision History ............................................................................... 2 Observation Receiver (ORx) ..................................................... 54 Specif icat ions ..................................................................................... 3 Sniffer Receiver (SnRx) ............................................................. 54 Current and Power Consumption Specifications ..................... 9 Clock Input .................................................................................. 54 Timing Specifications ................................................................ 10 Synthesizers ................................................................................. 55 Absolute Maximum Ratings .......................................................... 12 Serial Peripheral Interface (SPI) Interface .............................. 55 Reflow Profile .............................................................................. 12 GPIO x AND GPIO 3P3 x Pins ............................................ 55 Thermal Resistance .................................................................... 12 Auxiliary Converters .................................................................. 55 ESD Caution ................................................................................ 12 JESD204B Data Interface .......................................................... 55 Pin Configuration and Function Descriptions ........................... 13 Power Supply Sequence ............................................................. 56 Typical Performance Characteristics ........................................... 16 JTAG Boundary Scan ................................................................. 56 700 MHz Band ............................................................................ 16 Outline Dimensions ....................................................................... 57 2.6 GHz Band .............................................................................. 26 Ordering Guide .......................................................................... 57 3.5 GHz Band .............................................................................. 36 REVISION HISTORY 3/2017Rev. A to Rev. B Changes to Figure 105 Caption .................................................... 33 Table 1 ............................................................................. 6 Change to Changes to Figure 107 Caption .................................................... 34 Changes to Figure 115 Caption and Figure 116 Caption .......... 35 Deleted Figure 230 through Figure 239 Renumbered Changes to Figure 141 Caption .................................................... 40 Sequentially ..................................................................................... 55 Changes to Figure 164 Caption .................................................... 43 Changes to Sniffer Receiver (SnRx) Section ............................... 55 Changes to Figure 166 Caption .................................................... 44 Changes to Figure 174 Caption and Figure 175 ......................... 45 11/2016Rev. 0 to Rev. A Changes to Figure 194 and Figure 199 Caption ......................... 49 Changes to Table 1 ............................................................................ 6 Changes to Figure 222 Caption .................................................... 53 Changes to Table 2 ............................................................................ 9 Changes to Figure 224 Caption .................................................... 54 Changes to L3, L4 Description Column, Table 6 M3, M4 Added Figure 230 to Figure 235 Renumbered Sequentially .... 55 Description Column, Table 6 and M13, M14 Description Added Figure 236 to Figure 239 ................................................... 56 Column, Table 6 .............................................................................. 16 Added External LO Inputs Section .............................................. 58 Changes to Figure 46 Caption ....................................................... 23 Changes to Figure 48 Caption ....................................................... 24 7/2016Revision 0: Initial Version Changes to Figure 56 Caption and Figure 57 Caption .............. 25 Changes to Figure 82 Caption ....................................................... 30 Rev. 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