14-Output Clock Generator
AD9516-5
FEATURES FUNCTIONAL BLOCK DIAGRAM
CP
Low phase noise, phase-locked loop (PLL)
External VCO/VCXO to 2.4 GHz optional
1 differential or 2 single-ended reference inputs
REF1
STATUS
MONITOR
Reference monitoring capability
REFIN
Automatic revertive and manual reference
REFIN
REF2
switchover/holdover modes
Accepts LVPECL, LVDS, or CMOS references to 250 MHz
Programmable delays in path to PFD
CLK
DIVIDER
AND MUXes
Digital or analog lock detect, selectable CLK
Six 1.6 GHz LVPECL outputs, arranged in 3 groups
OUT0
DIV/ LVPECL
Each group shares a 1-to-32 divider with coarse phase delay
OUT1
OUT2
Additive output jitter: 225 fs rms
DIV/ LVPECL
OUT3
Channel-to-channel skew paired outputs of <10 ps
OUT4
DIV/ LVPECL
OUT5
Four 800 MHz LVDS outputs, arranged in 2 groups
t OUT6
DIV/ DIV/ LVDS/CMOS
Each group has 2 cascaded 1-to-32 dividers with coarse t OUT7
t OUT8
phase delay DIV/ DIV/ LVDS/CMOS
t OUT9
Additive output jitter: 275 fs rms
SERIAL CONTROL PORT
AND
Fine delay adjust (t) on each LVDS output AD9516-5
DIGITAL LOGIC
Each LVDS output can be reconfigured as two 250 MHz
CMOS outputs
Figure 1.
Automatic synchronization of all outputs on power-up
Manual output synchronization available
The AD9516-5 features six LVPECL outputs (in three pairs)
Available in 64-lead LFCSP
and four LVDS outputs (in two pairs). Each LVDS output can
APPLICATIONS be reconfigured as two CMOS outputs. The LVPECL outputs
operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and
Low jitter, low phase noise clock distribution
the CMOS outputs operate to 250 MHz.
10/40/100 Gb/sec networking line cards, including SONET,
Synchronous Ethernet, OTU2/3/4
Each pair of outputs has dividers that allow both the divide ratio
Forward error correction (G.710)
and coarse delay (or phase) to be set. The range of division for
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow
High performance wireless transceivers
a range of divisions up to a maximum of 1024.
ATE and high performance instrumentation
The AD9516-5 is available in a 64-lead LFCSP and can be
GENERAL DESCRIPTION operated from a single 3.3 V supply. An external VCO, which
1 requires an extended voltage range, can be accommodated by
The AD9516-5 provides a multi-output clock distribution function
connecting the charge pump supply (V ) to 5.5 V. A separate
CP
with subpicosecond jitter performance, along with an on-chip PLL
LVPECL power supply can be from 2.375 V to 3.6 V (nominal).
that can be used with an external VCO/VCXO of up to 2.4 GHz.
The AD9516-5 is specified for operation over the industrial
The AD9516-5 emphasizes low jitter and phase noise to
range of 40C to +85C.
maximize data converter performance, and it can benefit other
applications with demanding phase noise and jitter requirements.
For applications requiring an integrated EEPROM, or needing
additional outputs, the AD9520-5 and AD9522-5 are available.
1
AD9516 is used throughout the data sheet to refer to all members of the AD9516
family. However, when AD9516-5 is used, it refers to that specific member of the
AD9516 family.
Rev. A
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SWITCHOVER
AND MONITOR
PLL
07972-001AD9516-5
TABLE OF CONTENTS
Features .............................................................................................. 1 Typical Performance Characteristics ........................................... 18
Applications....................................................................................... 1 Terminology.................................................................................... 23
General Description ......................................................................... 1 Detailed Block Diagram ................................................................ 24
Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 25
Revision History ............................................................................... 3 Operational Configurations...................................................... 25
Specifications..................................................................................... 4 Lock Detect ................................................................................. 31
Power Supply Requirements ....................................................... 4 Clock Distribution ..................................................................... 35
PLL Characteristics ...................................................................... 4 Reset Modes ................................................................................ 43
Clock Inputs .................................................................................. 6 Power-Down Modes .................................................................. 43
Clock Outputs............................................................................... 6 Serial Control Port ......................................................................... 44
Clock Output Additive Phase Noise (Distribution Only; Serial Control Port Pin Descriptions....................................... 44
VCO Divider Not Used) .............................................................. 7
General Operation of Serial Control Port............................... 44
Clock Output Absolute Time Jitter (Clock Generation
Instruction Word (16 Bits)........................................................ 45
Using External VCXO) ................................................................ 8
MSB/LSB First Transfers ........................................................... 45
Clock Output Additive Time Jitter (VCO Divider
Thermal Performance.................................................................... 48
Not Used)....................................................................................... 8
Register Maps.................................................................................. 49
Clock Output Additive Time Jitter (VCO Divider Used) ....... 9
Register Map Overview ............................................................. 49
Delay Block Additive Time Jitter................................................ 9
Register Map Descriptions........................................................ 52
Serial Control Port ..................................................................... 10
Applications Information .............................................................. 71
PD RESET SYNC
, , and Pins ..................................................... 10
Frequency Planning Using the AD9516 .................................. 71
LD, STATUS, and REFMON Pins............................................ 11
Using the AD9516 Outputs for ADC Clock Applications .... 71
Power Dissipation....................................................................... 11
LVPECL Clock Distribution ..................................................... 72
Timing Characteristics .............................................................. 13
LVDS Clock Distribution.......................................................... 72
Absolute Maximum Ratings.......................................................... 15
CMOS Clock Distribution ........................................................ 73
Thermal Resistance .................................................................... 15
Outline Dimensions....................................................................... 74
ESD Caution................................................................................ 15
Ordering Guide .......................................................................... 74
Pin Configuration and Function Descriptions........................... 16
Rev. A | Page 2 of 76