6-Output Clock Generator with Integrated 1.6 GHz VCO Data Sheet AD9518-4 FEATURES FUNCTIONAL BLOCK DIAGRAM CP LF Low phase noise, phase-locked loop (PLL) On-chip VCO tunes from 1.45 GHz to 1.80 GHz External VCO/VCXO to 2.4 GHz optional REF1 STATUS 1 differential or 2 single-ended reference inputs MONITOR Reference monitoring capability REFIN VCO Automatic revertive and manual reference REF2 switchover/holdover modes Accepts LVPECL, LVDS, or CMOS references to 250 MHz DIVIDER CLK Programmable delays in path to PFD AND MUXs Digital or analog lock detect, selectable OUT0 3 pairs of 1.6 GHz LVPECL outputs DIV/ LVPECL OUT1 Each output pair shares a 1-to-32 divider with coarse OUT2 DIV/ LVPECL OUT3 phase delay OUT4 DIV/ LVPECL Additive output jitter: 225 fs rms OUT5 Channel-to-channel skew paired outputs of <10 ps SERIAL CONTROL PORT AND AD9518-4 Automatic synchronization of all outputs on power-up DIGITAL LOGIC Manual output synchronization available Available in a 48-lead LFCSP Figure 1. APPLICATIONS Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation GENERAL DESCRIPTION 1 The AD9518-4 provides a multi-output clock distribution In addition, the AD9516 and AD9517 are similar to the AD9518 function with subpicosecond jitter performance, along with an but have a different combination of outputs. on-chip PLL and VCO. The on-chip VCO tunes from 1.45 GHz Each pair of outputs has dividers that allow both the divide to 1.80 GHz. Optionally, an external VCO/VCXO of up to 2.4 ratio and coarse delay (or phase) to be set. The range of division GHz can be used. for the LVPECL outputs is 1 to 32. The AD9518-4 emphasizes low jitter and phase noise to maximize The AD9518-4 is available in a 48-lead LFCSP and can be data converter performance, and it can benefit other applications operated from a single 3.3 V supply. An external VCO, which with demanding phase noise and jitter requirements. requires an extended voltage range, can be accommodated by The AD9518-4 features six LVPECL outputs (in three pairs). connecting the charge pump supply (VCP) to 5 V. A separate The LVPECL outputs operate to 1.6 GHz. LVPECL power supply can be from 2.5 V to 3.3 V (nominal). For applications that require additional outputs, a crystal The AD9518-4 is specified for operation over the industrial reference input, zero-delay, or EEPROM for automatic range of 40C to +85C. configuration at startup, the AD9520 and AD9522 are available. 1 AD9518 is used throughout the data sheet to refer to all the members of the AD9518 family. However, when AD9518-4 is used, it refers to that specific member of the AD9518 family. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20072020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. SWITCHOVER AND MONITOR PLL 06433-001AD9518-4 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Resistance .................................................................... 13 Applications ...................................................................................... 1 ESD Caution ............................................................................... 13 Functional Block Diagram .............................................................. 1 Pin Configuration and Function Descriptions .......................... 14 General Description ......................................................................... 1 Typical Performance Characteristics .......................................... 16 Revision History ............................................................................... 3 Terminology .................................................................................... 20 Specifications .................................................................................... 4 Detailed Block Diagram ................................................................ 21 Power Supply Requirements ....................................................... 4 Theory of Operation ...................................................................... 22 PLL Characteristics ...................................................................... 4 Operational Configurations...................................................... 22 Clock Inputs .................................................................................. 6 Digital Lock Detect (DLD) ....................................................... 30 Clock Outputs ............................................................................... 6 Clock Distribution ..................................................................... 34 Timing Characteristics ................................................................ 6 Reset Modes ................................................................................ 38 Clock Output Additive Phase Noise (Distribution Only Power-Down Modes .................................................................. 39 VCO Divider Not Used).............................................................. 7 Serial Control Port ......................................................................... 40 Clock Output Absolute Phase Noise (Internal VCO Used) ... 7 Serial Control Port Pin Descriptions ....................................... 40 Clock Output Absolute Time Jitter (Clock Generation Using General Operation of Serial Control Port .............................. 40 Internal VCO) ............................................................................... 8 The Instruction Word (16 Bits) ............................................... 41 Clock Output Absolute Time Jitter (Clock Cleanup Using MSB/LSB First Transfers ........................................................... 41 Internal VCO) ............................................................................... 8 Thermal Performance .................................................................... 44 Clock Output Absolute Time Jitter (Clock Generation Using External VCXO) ........................................................................... 8 Control Registers ............................................................................ 45 Clock Output Additive Time Jitter (VCO Divider Not Used) Control Register Map Overview .............................................. 45 ......................................................................................................... 9 Control Register Map Descriptions ......................................... 47 Clock Output Additive Time Jitter (VCO Divider Used) ...... 9 Applications Information ............................................................. 59 Serial Control Port ..................................................................... 10 Frequency Planning Using the AD9518 ................................. 59 PD, SYNC, and RESET Pins ..................................................... 10 Using the AD9518 Outputs for ADC Clock Applications ... 59 LD, STATUS, and REFMON Pins ........................................... 11 LVPECL Clock Distribution ..................................................... 60 Power Dissipation ...................................................................... 11 Outline Dimensions ....................................................................... 61 Timing Diagrams ............................................................................ 12 Ordering Guide .......................................................................... 61 Absolute Maximum Ratings ......................................................... 13 Rev. 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