12 LVPECL/24 CMOS Output Clock Generator Data Sheet AD9520-5 FEATURES FUNCTIONAL BLOCK DIAGRAM CP Low phase noise, phase-locked loop (PLL) Optional external 3.3 V/5 V VCO/VCXO to 2.4 GHz 1 differential or 2 single-ended reference inputs STATUS REF1 MONITOR Accepts CMOS, LVDS, or LVPECL references to 250 MHz REFIN Accepts 16.62 MHz to 33.3 MHz crystal for reference input REFIN REF2 Optional reference clock doubler Reference monitoring capability ZERO DELAY Automatic/ manual reference holdover and reference CLK DIVIDER AND MUXES switchover modes, with revertive switching CLK LVPECL/ Glitch-free switchover between references CMOS OUT0 Automatic recovery from holdover DIV/ OUT1 OUT2 Digital or analog lock detect, selectable OUT3 Optional zero delay operation OUT4 DIV/ OUT5 Twelve 1.6 GHz LVPECL outputs divided into 4 groups OUT6 Each group of 3 outputs shares a 1-to-32 divider with OUT7 DIV/ OUT8 phase delay OUT9 Additive output jitter as low as 225 fs rms OUT10 DIV/ Channel-to-channel skew grouped outputs < 16 ps OUT11 Each LVPECL output can be configured as 2 CMOS outputs 2 SPI/I C CONTROL (for f 250 MHz) OUT PORT AND EEPROM AD9520-5 DIGITAL LOGIC Automatic synchronization of all outputs on power-up Manual output synchronization available Figure 1. SPI- and IC-compatible serial control port 64-lead LFCSP Nonvolatile EEPROM stores configuration settings APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10GFC, Synchronous Ethernet, OTU2/3/4 The AD9520-5 features 12 LVPECL outputs in four groups. Any Forward error correction (G.710) of the 1.6 GHz LVPECL outputs can be reconfigured as two Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs 250 MHz CMOS outputs. If an application requires LVDS High performance wireless transceivers ATE and high performance instrumentation drivers instead of LVPECL drivers, refer to the AD9522-5. Broadband infrastructures Each group of three outputs has a divider that allows both the divide ratio (from 1 to 32) and the phase offset or coarse time GENERAL DESCRIPTION delay to be set. 1 The AD9520-5 provides a multioutput clock distribution The AD9520-5 is available in a 64-lead LFCSP and can be operated function with subpicosecond jitter performance, along with from a single 3.3 V supply. The external VCO can have an an on-chip PLL that can be used with an external VCO. operating voltage of up to 5.5 V. A separate output driver power The AD9520-5 serial interface supports both SPI and IC ports. supply can be from 2.375 V to 3.465 V. An in-package EEPROM, which can be programmed through the The AD9520-5 is specified for operation over the standard serial interface, can store user-defined register settings for industrial range of 40C to +85C. power-up and chip reset. 1 AD9520 is used throughout this data sheet to refer to all the members of the AD9520 family. However, when AD9520-5 is used, it refers to that specific member of the AD9520 family. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20082016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com SWITCHOVER AND MONITOR PLL 07239-001AD9520-5 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Detailed Block Diagram ................................................................ 25 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 26 General Description ......................................................................... 1 Operational Configurations ...................................................... 26 Functional Block Diagram .............................................................. 1 Zero Delay Operation ................................................................ 37 Revision History ............................................................................... 3 Clock Distribution ..................................................................... 38 Specifications ..................................................................................... 4 Reset Modes ................................................................................ 43 Power Supply Requirements ....................................................... 4 Power-Down Modes .................................................................. 44 PLL Characteristics ...................................................................... 4 Serial Control Port ......................................................................... 45 Clock Inputs .................................................................................. 7 SPI/IC Port Selection ................................................................ 45 Clock Outputs ............................................................................... 7 IC Serial Port Operation .......................................................... 45 Timing Characteristics ................................................................ 8 SPI Serial Port Operation .......................................................... 48 Clock Output Additive Phase Noise (Distribution Only VCO SPI Instruction Word (16 Bits) ................................................. 49 Divider Not Used) ...................................................................... 10 SPI MSB/LSB First Transfers .................................................... 49 Clock Output Absolute Time Jitter (Clock Generation Using EEPROM Operations ..................................................................... 52 External VCXO) ......................................................................... 11 Writing to the EEPROM ........................................................... 52 Clock Output Additive Time Jitter (VCO Divider Not Used) Reading from the EEPROM ..................................................... 52 ....................................................................................................... 11 Programming the EEPROM Buffer Segment ......................... 53 Clock Output Additive Time Jitter (VCO Divider Used) ..... 12 Thermal Performance .................................................................... 54 Serial Control PortSPI Mode ................................................ 12 Register Map ................................................................................... 55 Serial Control PortIC Mode ................................................ 13 Register Map Descriptions ............................................................ 58 PD SYNC RESET , , EEPROM, and Pins .................................. 14 Applications Information .............................................................. 71 Serial Port Setup PinsSP1, SP0 ............................................. 14 Frequency Planning Using the AD9520 .................................. 71 LD, STATUS, and REFMON Pins ............................................ 14 Using the AD9520 Outputs for ADC Clock Applications .... 71 Power Dissipation ....................................................................... 15 LVPECL Clock Distribution ..................................................... 72 Absolute Maximum Ratings .......................................................... 16 CMOS Clock Distribution ........................................................ 72 Thermal Resistance .................................................................... 16 Outline Dimensions ....................................................................... 74 ESD Caution ................................................................................ 16 Ordering Guide .......................................................................... 74 Pin Configuration and Function Descriptions ........................... 17 Typical Performance Characteristics ........................................... 20 Terminology .................................................................................... 24 Rev. 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