12 LVDS/24 CMOS Output Clock Generator with Integrated 2.4 GHz VCO Data Sheet AD9522-1 FEATURES FUNCTIONAL BLOCK DIAGRAM CP LF Low phase noise, phase-locked loop (PLL) On-chip voltage controlled oscillator (VCO) tunes from 2.27 GHz to 2.65 GHz STATUS OPTIONAL REF1 MONITOR Supports external 3.3 V/5 V VCO/VCXO to 2.4 GHz REFIN VCO 1 differential or 2 single-ended reference inputs REFIN REF2 Accepts CMOS, LVPECL, or LVDS references to 250 MHz Accepts 16.62 MHz to 33.3 MHz crystal for reference input ZERO DELAY Optional reference clock doubler DIVIDER CLK AND MUXES Reference monitoring capability LVDS/ CMOS Revertive automatic and manual reference switchover/ OUT0 DIV/ OUT1 holdover modes OUT2 Glitch-free switchover between references OUT3 DIV/ OUT4 Automatic recovery from holdover OUT5 Digital or analog lock detect, selectable OUT6 DIV/ OUT7 Optional zero delay operation OUT8 Twelve 800 MHz LVDS outputs divided into 4 groups OUT9 DIV/ OUT10 Each group of 3 has a 1-to-32 divider with phase delay OUT11 Additive output jitter as low as 242 fs rms Channel-to-channel skew grouped outputs < 60 ps 2 SPI/I C CONTROL PORT AND EEPROM AD9522 Each LVDS output can be configured as 2 CMOS outputs DIGITAL LOGIC (for f 250 MHz) OUT Figure 1. Automatic synchronization of all outputs on power-up Manual synchronization of outputs as needed The AD9522 serial interface supports both SPI and I2C ports. SPI- and IC-compatible serial control port An in-package EEPROM can be programmed through the 64-lead LFCSP serial interface and store user-defined register settings for Nonvolatile EEPROM stores configuration settings power-up and chip reset. APPLICATIONS The AD9522 features 12 LVDS outputs in four groups. Any of the 800 MHz LVDS outputs can be reconfigured as two Low jitter, low phase noise clock distribution 250 MHz CMOS outputs. Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Each group of outputs has a divider that allows both the divide Forward error correction (G.710) ratio (from 1 to 32) and the phase (coarse delay) to be set. Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs The AD9522 is available in a 64-lead LFCSP and can be operated High performance wireless transceivers from a single 3.3 V supply. The external VCO can have an ATE and high performance instrumentation operating voltage up to 5.5 V. Broadband infrastructures The AD9522 is specified for operation over the standard industrial GENERAL DESCRIPTION range of 40C to +85C. 1 The AD9522-1 provides a multioutput clock distribution The AD9520-1 is an equivalent part to the AD9522-1 featuring function with subpicosecond jitter performance, along with an LVPECL/CMOS drivers instead of LVDS/CMOS drivers. on-chip PLL and VCO. The on-chip VCO tunes from 2.27 GHz to 2.65 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz can also be used. 1 The AD9522 is used throughout this data sheet to refer to all the members of the AD9522 family. However, when AD9522-1 is used, it is referring to that specific member of the AD9522 family. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20082015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. SWITCHOVER AND MONITOR PLL 07220-001AD9522-1 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Mode 1: Clock Distribution or External VCO < 1600 MHz .................................................................................................. 31 Applications ....................................................................................... 1 Mode 2: High Frequency Clock DistributionCLK or General Description ......................................................................... 1 External VCO > 1600 MHz .................................................. 33 Functional Block Diagram .............................................................. 1 Phase-Locked Loop (PLL) .................................................... 35 Revision History ............................................................................... 4 Configuration of the PLL ...................................................... 35 Specifications ..................................................................................... 5 Phase Frequency Detector (PFD) ........................................ 35 Power Supply Requirements ....................................................... 5 Charge Pump (CP) ................................................................. 35 PLL Characteristics ...................................................................... 5 On-Chip VCO ........................................................................ 36 Clock Inputs .................................................................................. 8 PLL External Loop Filter ....................................................... 36 Clock Outputs ............................................................................... 8 PLL Reference Inputs ............................................................. 36 Timing Characteristics ................................................................ 9 Reference Switchover ............................................................. 37 Timing Diagrams ..................................................................... 9 Reference Divider R ............................................................... 37 Clock Output Additive Phase Noise (Distribution Only VCO VCO/VCXO Feedback Divider N: P, A, B .......................... 37 Divider Not Used) ...................................................................... 10 Digital Lock Detect (DLD) ................................................... 39 Clock Output Absolute Phase Noise (Internal VCO Used) .. 11 Analog Lock Detect (ALD) ................................................... 39 Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO) ............................................................................. 11 Current Source Digital Lock Detect (CSDLD) .................. 39 Clock Output Absolute Time Jitter (Clock Cleanup Using External VCXO/VCO Clock Input (CLK/CLK) ................ 40 Internal VCO) ............................................................................. 11 Holdover .................................................................................. 40 Clock Output Absolute Time Jitter (Clock Generation Using External/Manual Holdover Mode ........................................ 40 External VCXO) ......................................................................... 12 Automatic/Internal Holdover Mode .................................... 40 Clock Output Additive Time Jitter (VCO Divider Not Used) Frequency Status Monitors ................................................... 42 ....................................................................................................... 12 VCO Calibration .................................................................... 42 Clock Output Additive Time Jitter (VCO Divider Used) ..... 12 Zero Delay Operation ................................................................ 45 Serial Control PortSPI Mode ................................................ 13 Internal Zero Delay Mode..................................................... 45 Serial Control PortIC Mode ................................................ 13 External Zero Delay Mode .................................................... 45 PD SYNC RESET , , and Pins ..................................................... 14 Clock Distribution ..................................................................... 46 Serial Port Setup Pins: SP1, SP0 ............................................... 14 Operation Modes ................................................................... 46 LD, STATUS, and REFMON Pins ............................................ 15 Clock Frequency Division ..................................................... 47 Power Dissipation ....................................................................... 15 VCO Divider ........................................................................... 47 Absolute Maximum Ratings .......................................................... 17 Channel Dividers ................................................................... 47 Thermal Resistance .................................................................... 17 Synchronizing the OutputsSYNC Function ................... 49 ESD Caution ................................................................................ 17 LVDS Output Drivers ............................................................ 50 Pin Configuration and Function Descriptions ........................... 18 CMOS Output Drivers .......................................................... 51 Typical Performance Characteristics ........................................... 21 Reset Modes ................................................................................ 51 Test Circuits ..................................................................................... 26 Power-On Reset ...................................................................... 51 Terminology .................................................................................... 27 RESET Hardware Reset via the Pin ..................................... 51 Detailed Block Diagram ................................................................ 28 Soft Reset via the Serial Port ................................................. 51 Theory of Operation ...................................................................... 29 Soft Reset to Settings in EEPROM when EEPROM Pin = 0 via Operational Configurations ...................................................... 29 the Serial Port ......................................................................... 51 Mode 0: Internal VCO and Clock Distribution ................. 29 Rev. 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