Jitter Cleaner and Clock Generator with 14 Differential or 29 LVCMOS Outputs Data Sheet AD9523 FEATURES FUNCTIONAL BLOCK DIAGRAM Output frequency: <1 MHz to 1 GHz OSC IN, OSC IN Start-up frequency accuracy: <100 ppm (determined by VCXO reference accuracy) REFA, AD9523 REFA Zero delay operation OUT0, REFB, PLL1 PLL2 OUT0 Input-to-output edge timing: <150 ps REFB 14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS REF TEST OUT1, OUT1 14 dedicated output dividers with jitter-free adjustable delay Adjustable delay: 63 resolution steps of period of VCO SCLK/SCL output divider CONTROL OUT12, SDIO/SDA INTERFACE Output-to-output skew: <50 ps OUT12 2 (SPI AND I C) SDO ZERO Duty cycle correction for odd divider settings OUT13, DELAY OUT13 Automatic synchronization of all outputs on power-up 14-CLOCK Absolute output jitter: <200 fs at 122.88 MHz EEPROM DISTRIBUTION Integration range: 12 kHz to 20 MHz Distribution phase noise floor: 160 dBc/Hz ZD IN, ZD IN Digital lock detect Figure 1. Nonvolatile EEPROM stores configuration settings SPI- and IC-compatible serial control port GENERAL DESCRIPTION Dual PLL architecture The AD9523 provides a low power, multi-output, clock distribution PLL1 function with low jitter performance, along with an on-chip PLL Low bandwidth for reference input clock cleanup with and VCO. The on-chip VCO tunes from 3.6 GHz to 4.0 GHz. external VCXO The AD9523 is designed to support the clock requirements for long Phase detector rate up to130 MHz term evolution (LTE) and multicarrier GSM base station designs. Redundant reference inputs It relies on an external VCXO to provide the reference jitter cleanup Automatic and manual reference switchover modes to achieve the restrictive low phase noise requirements necessary Revertive and nonrevertive switching for acceptable data converter SNR performance. Loss of reference detection with holdover mode Low noise LVCMOS output from VCXO used for RF/IF The input receivers, oscillator, and zero delay receiver provide synthesizers both single-ended and differential operation. When connected PLL2 to a recovered system reference clock and a VCXO, the device Phase detector rate up to 259 MHz generates 14 low noise outputs with a range of 1 MHz to 1 GHz, Integrated low noise VCO and one dedicated buffered output from the input PLL (PLL1). The frequency and phase of one clock output relative to another APPLICATIONS clock output can be varied by means of a divider phase select LTE and multicarrier GSM base stations function that serves as a jitter-free coarse timing adjustment in Wireless and broadband infrastructure increments that are equal to half the period of the signal coming Medical instrumentation out of the VCO. Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs An in-package EEPROM can be programmed through the serial Low jitter, low phase noise clock distribution interface to store user-defined register settings for power-up and Clock generation and translation for SONET, 10Ge, 10G FC, chip reset. and other 10 Gbps protocols Forward error correction (G.710) High performance wireless transceivers ATE and high performance instrumentation Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20102015 Analog Devices, Inc. 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Technical Support www.analog.com 08439-001AD9523 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 19 Applications ....................................................................................... 1 Detailed Block Diagram ............................................................ 19 Functional Block Diagram .............................................................. 1 Overview ..................................................................................... 19 General Description ......................................................................... 1 Component BlocksInput PLL (PLL1) .................................. 20 Revision History ............................................................................... 3 Component BlocksOutput PLL (PLL2) .............................. 22 Specifications ..................................................................................... 4 Clock Distribution ..................................................................... 24 Conditions ..................................................................................... 4 Zero Delay Operation ................................................................ 26 Supply Current .............................................................................. 4 Lock Detect ................................................................................. 26 Power Dissipation ......................................................................... 5 Reset Modes ................................................................................ 26 REFA, REFA, REFB, REFB, OSC IN, OSC IN, and ZD IN, Power-Down Mode .................................................................... 27 ZD IN Input Characteristics ...................................................... 5 Power Supply Sequencing ......................................................... 27 OSC CTRL Output Characteristics .......................................... 6 Serial Control Port ......................................................................... 28 REF TEST Input Characteristics ............................................... 6 SPI/IC Port Selection ................................................................ 28 PLL1 Characteristics .................................................................... 6 IC Serial Port Operation .......................................................... 28 PLL1 Output Characteristics ...................................................... 6 SPI Serial Port Operation .......................................................... 31 Distribution Output Characteristics (OUT0, OUT0 to SPI Instruction Word (16 Bits) ................................................. 32 OUT13, OUT13) .......................................................................... 7 SPI MSB/LSB First Transfers .................................................... 32 Timing Alignment Characteristics ............................................ 8 EEPROM Operations ..................................................................... 35 Jitter and Noise Characteristics .................................................. 8 Writing to the EEPROM ........................................................... 35 PLL2 Characteristics .................................................................... 8 Reading from the EEPROM ..................................................... 35 PD RESET Logic Input Pins , EEPROM SEL, REF SEL, , Programming the EEPROM Buffer Segment ......................... 36 SYNC .............................................................................................. 9 Device Initialization Flow Charts ................................................. 38 Status Output PinsSTATUS1, STATUS0 ............................... 9 Power Dissipation and Thermal Considerations ....................... 41 Serial Control PortSPI Mode .................................................. 9 Clock Speed and Driver Mode ................................................. 41 Serial Control PortIC Mode ................................................ 10 Evaluation of Operating Conditions ........................................ 41 Absolute Maximum Ratings .......................................................... 11 Thermally Enhanced Package Mounting Guidelines ............ 42 Thermal Resistance .................................................................... 11 Control Registers ............................................................................ 43 ESD Caution ................................................................................ 11 Control Register Map ................................................................ 43 Pin Configuration and Function Descriptions ........................... 12 Control Register Map Bit Descriptions ................................... 48 Typical Performance Characteristics ........................................... 15 Outline Dimensions ....................................................................... 60 Input/Output Termination Recommendations .......................... 17 Ordering Guide .......................................................................... 60 Terminology .................................................................................... 18 Rev. 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