JESD204B Clock Generator with 14 LVDS/HSTL Outputs Data Sheet AD9528 FEATURES FUNCTIONAL BLOCK DIAGRAM 14 outputs configurable for HSTL or LVDS VXCO IN Maximum output frequency 6 outputs up to 1.25 GHz 8 outputs up to 1 GHz REFA Dependent on the voltage controlled crystal oscillator REFB PLL1 PLL2 OUT0/ OUT0 (VCXO) frequency accuracy (start-up frequency accuracy: REF SEL <100 ppm) Dedicated 8-bit dividers on each output OUT13/ SYSREF Coarse delay: 63 steps at 1/2 the period of the RF VCO OUT13 JESD204B SYSREF REQ divider output frequency with no jitter impact Fine delay: 15 steps of 31 ps resolution CONTROL CLOCK Typical output to output skew: 20 ps INTERFACE DISTRIBUTION 2 AD9528 (SPI AND I C) 14 OUTPUTS Duty cycle correction for odd divider settings Output 12 and Output 13, VCXO output at power-up Figure 1. Absolute output jitter: <160 fs at 122.88 MHz, 12 kHz to GENERAL DESCRIPTION 20 MHz integration range Digital frequency lock detect The AD9528 is a two-stage PLL with an integrated JESD204B 2 SPI- and I C-compatible serial control port SYSREF generator for multiple device synchronization. The Dual PLL architecture first stage phase-locked loop (PLL) (PLL1) provides input PLL1 reference conditioning by reducing the jitter present on a Provides reference input clock cleanup with external VCXO system clock. The second stage PLL (PLL2) provides high Phase detector rate up to 110 MHz frequency clocks that achieve low integrated jitter as well as low Redundant reference inputs broadband noise from the clock output drivers. The external Automatic and manual reference switchover modes VCXO provides the low noise reference required by PLL2 to Revertive and nonrevertive switching achieve the restrictive phase noise and jitter requirements Loss of reference detection with holdover mode necessary to achieve acceptable performance. The on-chip VCO Low noise LVDS/HSTL outputs from VCXO used for radio tunes from 3.450 GHz to 4.025 GHz. The integrated SYSREF frequency/intermediate frequency (RF/IF) synthesizers generator outputs single shot, N-shot, or continuous signals PLL2 synchronous to the PLL1 and PLL2 outputs to time align Phase detector rate of up to 275 MHz multiple devices. Integrated low noise VCO The AD9528 generates six outputs (Output 0 to Output 3, Output 12, and Output 13) with a maximum frequency of APPLICATIONS 1.25 GHz, and eight outputs with a maximum frequency of up High performance wireless transceivers to 1 GHz. Each output can be configured to output directly LTE and multicarrier GSM base stations from PLL1, PLL2, or the internal SYSREF generator. Each of Wireless and broadband infrastructure the 14 output channels contains a divider with coarse digital Medical instrumentation phase adjustment and an analog fine phase delay block that Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs allows complete flexibility in timing alignment across all 14 supports JESD204B outputs. The AD9528 can also be used as a dual input flexible Low jitter, low phase noise clock distribution buffer to distribute 14 device clock and/or SYSREF signals. At ATE and high performance instrumentation power-up, the AD9528 sends the VCXO signal directly to Output 12 and Output 13 to serve as the power-up ready clocks. Note that, throughout this data sheet, the dual function pin names are referenced by the relevant function where applicable. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20142020 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 12380-001AD9528 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 25 Applications ...................................................................................... 1 Detailed Block Diagram ............................................................ 25 Functional Block Diagram .............................................................. 1 Overview ...................................................................................... 25 General Description ......................................................................... 1 Component BlocksPLL1 ....................................................... 26 Revision History ............................................................................... 3 Component BlocksPLL2 ....................................................... 27 Specifications .................................................................................... 4 Clock Distribution ..................................................................... 29 Conditions ..................................................................................... 4 SYSREF Operation ......................................................................... 32 Supply Current ............................................................................. 4 SYSREF Signal Path ................................................................... 32 Power Dissipation ........................................................................ 5 SYSREF Generator ..................................................................... 34 Input CharacteristicsREFA, REFA, REFB, REFB, Serial Control Port ......................................................................... 35 2 VCXO IN, VCXO IN, SYSREF IN, and SYSREF IN .......... 6 SPI/I C Port Selection ................................................................ 35 PLL1 Characteristics .................................................................... 6 SPI Serial Port Operation .......................................................... 35 2 VCXO VT Output Characteristics ........................................... 7 I C Serial Port Operation .......................................................... 38 PLL2 Characteristics .................................................................... 7 Device Initialization and Calibration Flowcharts ...................... 41 Clock Distribution Output Characteristics .............................. 7 Power Dissipation and Thermal Considerations ...................... 46 Output Timing Alignment Characteristics .............................. 8 Clock Speed and Driver Mode ................................................. 46 SYSREF IN, SYSREF IN, VCXO IN, and VCXO IN Evaluation of Operating Conditions ....................................... 46 Timing Characteristics ................................................................ 8 Thermally Enhanced Package Mounting Guidelines ........... 47 Clock Output Absolute Phase NoiseDual Loop Mode ....... 9 Control Register Map .................................................................... 48 Clock Output Absolute Phase NoiseSingle Loop Mode ... 10 Control Register Map Bit Descriptions ....................................... 52 Clock Output Absolute Time Jitter ......................................... 11 Serial Control Port Configuration (Register 0x0000 to Clock Output Additive Time Jitter (Buffer Mode) ................ 12 Register 0x0001) ......................................................................... 52 Logic Input PinsRESET, REF SEL, and SYSREF REQ ... 12 Clock Part Family ID (Register 0x0003 to Register 0x0006) 53 Status Output PinsSTATUS0 and STATUS1 ..................... 12 SPI Version (Register 0x000B) ................................................. 53 Serial Control PortSerial Port Interface (SPI) Mode ......... 13 Vendor ID (Register 0x000C to Register 0x000D) ................ 53 2 Serial Control PortI C Mode ................................................ 14 IO UPDATE (Register 0x000F) .............................................. 53 Absolute Maximum Ratings ......................................................... 15 PLL1 Control (Register 0x0100 to Register 0x010B) ............ 54 Thermal Resistance .................................................................... 15 PLL2 (Register 0x0200 to Register 0x0209) ............................ 56 ESD Caution................................................................................ 15 Clock Distribution (Register 0x300 to Register 0x0329) ...... 59 Pin Configuration and Function Descriptions .......................... 16 Power-Down Control (Register 0x0500 to Register 0x0504)63 Typical Performance Characteristics ........................................... 19 Status Control (Register 0x0505 to Register 0x0509)............ 65 Input/Output Termination Recommendations ......................... 22 Outline Dimensions ....................................................................... 67 Typical Application Circuit .......................................................... 23 Ordering Guide .......................................................................... 67 Terminology .................................................................................... 24 Rev. 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