3-Channel Clock Generator, 24 Outputs Data Sheet AD9531 FEATURES GENERAL DESCRIPTION 3 fully integrated PLL/VCO cores (PLL1, PLL2, and PLL3) The AD9531 provides a multioutput clock generator function Jitter performance: 0.462 ps rms typical and three on-chip phase-locked loop (PLL) cores with SPI PLL1, fractional-N mode, 12 kHz to 20 MHz bandwidth programmable output frequencies and formats. Loss of reference and lock detection for each PLL PLL1 provides two reference inputs and 10 outputs and includes Pin-configurable common frequency translations four user selectable loop configurations. The PLL has a fully Automatic synchronization of all outputs on power-up integrated loop filter requiring only a single external capacitor Manual output synchronization capability (or a series RC network). PLL1 provides a wide range of output Package available in an 88-lead LFCSP frequencies up to 400 MHz and is capable of operating with an PLL1 details external voltage controlled crystal oscillator (VCXO) and loop Fractional-N/integer-N modes filter, instead of the integrated voltage controlled oscillator Optional external VCXO (VCO) and loop filter. Fixed delay mode for constant static phase offset PLL2 is an integer-N PLL providing a single reference input and 2 reference clock inputs 12 outputs. PLL2 synthesizes output frequencies up to 400 MHz Input format: differential/single-ended from the REF2 x source and synchronizes the output clocks to Frequency range: 9.5 MHz to 260 MHz the input reference. Reference switching: manual/automatic 10 ultralow jitter HSTL/CMOS outputs up to 400 MHz PLL3 provides a single reference input and two outputs. PLL3 PLL2 details synthesizes output frequencies up to 400 MHz from the REF3 x Integer-N mode (1 reference clock input) source and synchronizes the output clocks to input reference. 1 Input format: differential/single-ended/crystal The AD9531 is available in an 88-lead LFCSP and is specified Frequency range: 9.5 MHz to 250 MHz over the 40C to +85C operating temperature range. 12 HSTL/CMOS outputs up to 400 MHz Throughout this data sheet, multifunction pins, such as PLL3 details LOR/M4, are referred to either by the entire pin name or by a Integer-N mode (1 reference clock input) single function of the pin (for example, LOR, when only that Frequency range: 9.5 MHz to 100 MHz function is relevant). In other cases, the text and figures of this Input format: differential/crystal (supports a 25 MHz to data sheet contain references to a channel rather than a pin. For 50 MHz AT-cut quartz crystal resonator) 2 HSTL/LVDS/CMOS outputs to 400 MHz/150 MHz example, REF A refers to the REF A channel rather than the (differential/CMOS) REF AP and REF AN pins. Likewise, OUT3 1 refers to Channel 1 of PLL3 rather than the OUT3 1P and OUT3 1N pins. APPLICATIONS Additionally, an abbreviated notation for a pin pair replaces an Radio equipment controller clocking explicit reference to a each pin (for example, REF Ax signifies Low jitter/phase noise clock generation and distribution the REF AN and REF AP pins.). Clock generation and translation for SONET, 10GE, 10G FC, and other 10 Gbps protocols 40 Gbps/100 Gbps networking line cards, including SONET, synchronous ethernet, OTU2/3/4 Forward error correction (G.710) High performance wireless transceivers ATE and high performance instrumentation Broadband infrastructures Ethernet line cards, switches, and routers SATA and PCI-express Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. AD9531 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 PLL2Integer-N PLL ................................................................ 41 Applications ................................................................................... 1 PLL2 Reference Clock Input (REF2 P/REF2 N) .................. 41 General Description ......................................................................... 1 PLL2 Reference Divider (R2) .................................................... 41 Revision History ............................................................................... 3 PLL2 PFD and Charge Pump ................................................... 41 Functional Block Diagram .............................................................. 4 PLL2 Loop Filter ......................................................................... 42 Specifications ..................................................................................... 5 PLL2 VCO ................................................................................... 42 Conditions ..................................................................................... 5 PLL2 VCO Divider (M2) ........................................................... 44 Supply Current .............................................................................. 5 PLL2 Feedback Divider (N2) .................................................... 44 Power Dissipation ......................................................................... 6 PLL2 Clock Distribution ........................................................... 44 LDET1/M1, LDET2/M2, LDET3/M3, and LOR/M4 Pins ...... 8 PLL3 Integer-N PLL ................................................................... 46 REF1 SEL Pin ............................................................................... 8 PLL3 Reference Clock Input (REF3 P/REF3 N) .................. 46 PLL1 Characteristics .................................................................... 8 PLL3 Input Frequency Scaling ................................................. 46 PLL2 Characteristics .................................................................. 13 PLL3 PFD and Charge Pumps .................................................. 46 PLL3 Characteristics .................................................................. 17 PLL3 Loop Filters ....................................................................... 47 Serial Control Port ..................................................................... 20 PLL3 VCOs ................................................................................. 47 Absolute Maximum Ratings .......................................................... 21 PLL3 Feedback Dividers ............................................................ 47 ESD Caution ................................................................................ 21 PLL3B Reference Divider (R3B) .............................................. 47 Pin Configuration and Function Descriptions ........................... 22 PLL3 Clock Distribution ........................................................... 47 Typical Performance Characteristics ........................................... 25 Additional Features ........................................................................ 49 PLL1 Characteristics .................................................................. 25 Power-On Reset (POR) ............................................................. 49 PLL2 Characteristics .................................................................. 26 ROM Profiles .............................................................................. 49 PLL3 Characteristics .................................................................. 27 Multifunction Pins (LDET1/M1, LDET2/M2, LDET3/M3, LOR/M4) ..................................................................................... 49 General Characteristics ............................................................. 28 Loss of Reference (LOR)............................................................ 50 Terminology .................................................................................... 29 PLL Lock Detection (LDETx) .................................................. 51 Theory of Operation ...................................................................... 30 Automatic Output Synchronization ........................................ 51 PLL1Integer/Fractional-N PLL ............................................ 30 Serial Control Port ......................................................................... 54 PLL1 Loop Configurations........................................................ 31 Serial Control Port Pin Descriptions ....................................... 54 PLL1 Reference Clock Inputs (REF1 Ax/REF1 Bx)............. 34 Operation of the Serial Control Port ....................................... 54 PLL1 Reference Frequency Scaling .......................................... 34 Instruction Word (16 Bits) ........................................................ 55 PLL1 Phase Frequency Detector (PFD) and Charge Pumps ..... 35 MSB/LSB First Transfers ........................................................... 55 PLL1 Loop Filter ......................................................................... 35 Register Map ................................................................................... 57 PLL1 Internal VCO .................................................................... 35 Register Map Details ...................................................................... 60 PLL1 VCO Divider (M1) ........................................................... 35 Serial Port Control RegistersRegister 0x0000 to Register PLL1 External VCXO Input (RFIN1 x) .................................. 35 0x0005 .......................................................................................... 60 PLL1 Clock Distribution ........................................................... 36 Device Identification and ROM Profile RegistersRegister PLL1 Holdover Mode and Freerun Mode ............................... 37 0x000A to Register 0x000E ....................................................... 60 PLL1 Reference SelectionManual and Automatic ............. 37 Status RegistersRegister 0x0080 to Register 0x0082 .......... 61 PLL1 Internal VCO Calibration ............................................... 38 LDET/LOR Control RegistersRegister 0x0083 to Register PLL1 - Modulator .................................................................. 40 0x0085 .......................................................................................... 61 PLL1 Lock Detector ................................................................... 40 PLL1 Registers ............................................................................ 62 Rev. 0 Page 2 of 88