655 MHz Low Jitter Clock Generator Data Sheet AD9540 FEATURES APPLICATIONS Excellent intrinsic jitter performance Clocking high performance data converters 200 MHz phase frequency detector inputs Base station clocking applications 655 MHz programmable input dividers for the phase Network (SONET/SDH) clocking frequency detector (M, N) M, N = 1 to 16 (bypassable) Gigabit Ethernet (GbE) clocking Programmable RF divider (R) R = 1, 2, 4, 8 (bypassable) Instrumentation clocking circuits 8 programmable phase/frequency profiles Agile LO frequency synthesis 400 MSPS internal DDS clock speed Automotive radar 48-bit frequency tuning word resolution FM chirp source for radar and scanning systems 14-bit programmable phase offset Test and measurement equipment 1.8 V supply for device operation Acousto-optic device drivers 3.3 V supply for I/O, CML driver, and charge pump output Software controlled power-down 48-lead LFCSP package Programmable charge pump current (up to 4 mA) Dual-mode PLL lock detect 655 MHz CML-mode PECL-compliant output driver FUNCTIONAL BLOCK DIAGRAM AVDD AGND DVDD DGND CP VDD CP RSET CP REF, AMP REFIN M DIVIDER PHASE REFIN CHARGE CP OUT FREQUENCY PUMP DETECTOR N DIVIDER CLK2 SYNC, PLL SYNC IN/STATUS LOCK CLK2 CLK1 DRV RSET CML CLK1 OUT0 DIVIDER 1, 2, 4, 8 OUT0 SCLK SERIAL SDI/O CONTROL AD9540 SDO PORT CS CLK TIMING AND DIVCLK CONTROL LOGIC S2 48 PHASE/ IOUT 10 S1 FREQUENCY DDS DAC 14 PROFILES IOUT S0 DAC RSET Figure 1. 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Trademarks and registered trademarks are the property of their respective owners. 04947-001AD9540 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 PLL Circuitry .............................................................................. 19 Applications ...................................................................................... 1 CML Driver ................................................................................. 19 Functional Block Diagram .............................................................. 1 DDS and DAC ............................................................................ 20 Revision History ............................................................................... 2 Modes of Operation ....................................................................... 21 Product Overview ............................................................................. 3 Selectable Clock Frequencies and Selectable Edge Delay ..... 21 Specifications .................................................................................... 4 Synchronization Modes for Multiple Devices ............................. 21 Loop Measurement Conditions ................................................. 8 Serial Port Operation ..................................................................... 22 Absolute Maximum Ratings ........................................................... 9 Instruction Byte .......................................................................... 23 ESD Caution.................................................................................. 9 Serial Interface Port Pin Description ...................................... 23 Pin Configuration and Function Descriptions .......................... 10 MSB/LSB Transfers .................................................................... 23 Typical Performance Characteristics ........................................... 12 Register Map and Description ...................................................... 24 Typical Application Circuits ......................................................... 17 Control Register Bit Descriptions ............................................ 27 Application Circuit Descriptions ............................................. 18 Outline Dimensions ....................................................................... 32 Theory of Operation ...................................................................... 19 Ordering Guide .......................................................................... 32 REVISION HISTORY 9/2020Rev. C to Rev. D 9/2016Rev. A to Rev. B Changed CP-48-1 to CP-48-4 ...................................... Throughout Change to Features ............................................................................ 1 Changes to Figure 3 ........................................................................ 10 Updated Outline Dimensions ...................................................... 32 Updated Outline Dimensions ....................................................... 33 Changes to Ordering Guide .......................................................... 32 Changes to Ordering Guide .......................................................... 33 2/2006Rev. 0 to Rev. A 4/2018Rev. B to Rev. C Changes to Features Section ............................................................ 1 Changes to Figure 3 ........................................................................ 10 Changes to Applications Section .................................................... 1 Updated Outline Dimensions ....................................................... 32 Changes to Functional Block Diagram .......................................... 1 Changes to Ordering Guide .......................................................... 32 Changes to Table 1 ............................................................................ 4 Changes to Typical Application Circuits Section ...................... 17 Updates to Ordering Guide .......................................................... 32 7/2004Revision 0: Initial Version Rev. D Page 2 of 32