Dual/Quad Input Network Clock Generator/Synchronizer Data Sheet AD9547 FEATURES APPLICATIONS Supports Stratum 2 stability in holdover mode Network synchronization Supports reference switchover with phase build-out Cleanup of reference clock jitter Supports hitless reference switchover SONET/SDH clocks up to OC-192, including FEC Automatic/manual holdover and reference switchover Stratum 2 holdover, jitter cleanup, and phase transient 2 pairs of reference input pins, with each pair configurable control as a single differential input or as 2 independent single- Stratum 3E and Stratum 3 reference clocks ended inputs Wireless base stations, controllers Input reference frequencies from 1 kHz to 750 MHz Cable infrastructure Reference validation and frequency monitoring (1 ppm) Data communications Programmable input reference switchover priority 30-bit programmable input reference divider GENERAL DESCRIPTION 2 pairs of clock output pins, with each pair configurable as The AD9547 provides synchronization for many systems, a single differential LVDS/LVPECL output or as 2 single- including synchronous optical networks (SONET/SDH). The ended CMOS outputs AD9547 generates an output clock that is synchronized to one Output frequencies up to 450 MHz of two differential or four single-ended external input references. 20-bit integer and 10-bit fractional programmable feedback The digital PLL allows for reduction of input time jitter or phase divider noise associated with the external references. The AD9547 Programmable digital loop filter covering loop bandwidths continuously generates a clean (low jitter), valid output clock, from 0.001 Hz to 100 kHz even when all references fail, by means of digitally controlled Optional low noise LC-VCO system clock multiplier loop and holdover circuitry. Optional crystal resonator for system clock input The AD9547 operates over an industrial temperature range of On-chip EEPROM to store multiple power-up profiles 40C to +85C. Software controlled power-down 64-lead LFCSP package FUNCTIONAL BLOCK DIAGRAM STABLE ANALOG SOURCE FILTER AD9547 CLOCK MULTIPLIER CLOCK DISTRIBUTION CHANNEL 0 DIVIDER DIGITAL DAC CHANNEL 1 PLL DIVIDER REFERENCE INPUTS AND MONITOR MUX SYNC SERIAL CONTROL INTERFACE STATUS AND EEPROM 2 (SPI or I C) CONTROL PINS Figure 1. Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20092014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 08300-001AD9547 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Digital Phase-Locked Loop (DPLL) Core ............................... 32 Applications ....................................................................................... 1 Direct Digital Synthesizer (DDS) ............................................. 34 General Description ......................................................................... 1 Tuning Word Processing ........................................................... 35 Functional Block Diagram .............................................................. 1 Loop Control State Machine ..................................................... 36 Revision History ............................................................................... 3 System Clock Inputs ................................................................... 37 Specif icat ions ..................................................................................... 4 SYSCLK PLL Multiplier ............................................................. 38 Supply Voltage ............................................................................... 4 Clock Distribution ..................................................................... 39 Supply Current .............................................................................. 4 Status and Control .......................................................................... 44 Power Dissipation ......................................................................... 4 Multifunction Pins (M0 to M7) ............................................... 44 Logic Inputs (M0 to M7, RESET) ............................................... 5 IRQ Pin ........................................................................................ 45 Logic Outputs (M0 to M7, IRQ) ................................................ 5 Watchdog Timer ......................................................................... 45 System Clock Inputs (SYSCLKP, SYSCLKN)............................ 5 EEPROM ..................................................................................... 46 Distribution Clock Inputs (CLKINP, CLKINN) ...................... 6 Serial Control Port ......................................................................... 51 2 Reference Inputs (REFA/REFAA, REFB/REFBB) .................... 7 SPI/I C Port Selection ................................................................ 51 Reference Monitors ...................................................................... 7 SPI Serial Port Operation .......................................................... 51 2 Reference Switchover Specifications .......................................... 8 I C Serial Port Operation .......................................................... 56 Distribution Clock Outputs (OUT0, OUT1) ........................... 8 I/O Programming Registers .......................................................... 59 DAC Output Characteristics (DACOUTP, DACOUTN) ....... 9 Buffered/Active Registers .......................................................... 59 Time Duration of Digital Functions ........................................ 10 Autoclearing Registers ............................................................... 59 Digital PLL .................................................................................. 10 Register Access Restrictions ...................................................... 59 Digital PLL Lock Detection ...................................................... 10 Register Map ................................................................................... 60 Holdover Specifications ............................................................. 10 Register Bit Descriptions ............................................................... 70 Serial Port SpecificationsSPI Mode ...................................... 11 Serial Port Configuration and Part Identification 2 (Register 0x0000 to Register 0x0005) ...................................... 70 Serial Port SpecificationsI C Mode ...................................... 12 System Clock (SYSCLK) (Register 0x0100 to Jitter Generation ......................................................................... 13 Register 0x0108).......................................................................... 71 Absolute Maximum Ratings .......................................................... 14 General Configuration (Register 0x0200 to ESD Caution ................................................................................ 14 Register 0x0214).......................................................................... 72 Pin Configuration and Function Descriptions ........................... 15 DPLL Configuration (Register 0x0300 to Register 0x031B) ..... 75 Typical Performance Characteristics ........................................... 18 Clock Distribution Output Configuration (Register 0x0400 Input/Output Termination Recommendations .......................... 23 to Register 0x0417) .................................................................. 77 Getting Started ................................................................................ 24 Reference Input Configuration (Register 0x0500 to Register 0x0507) .......................................................................... 79 Power-On Reset .......................................................................... 24 Profile Registers (Register 0x0600 to Register 0x07FF) ........ 81 Initial M0 to M7 Pin Programming ......................................... 24 Operational Controls (Register 0x0A00 to Device Register Programming .................................................. 24 Register 0x0A10)......................................................................... 90 Theory of Operation ...................................................................... 26 Clock Part Serial ID (Register 0x0C00 to Register 0x0C07) ..... 94 O ver vie w ...................................................................................... 26 Status Readback (Register 0x0D00 to Register 0x0D19) ...... 95 Reference Clock Inputs .............................................................. 27 Nonvolatile Memory (EEPROM) Control (Register 0x0E00 Reference Monitors .................................................................... 27 to Register 0x0E03) .................................................................... 97 Reference Profiles ....................................................................... 28 EEPROM Storage Sequence (Register 0x0E10 to Reference Switchover ................................................................. 30 Register 0x0E3F) .......................................................................... 98 Rev. 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