Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator Data Sheet AD9554-1 FEATURES APPLICATIONS Supports GR-1244 Stratum 3 stability in holdover mode Network synchronization, including synchronous Ethernet Supports smooth reference switchover with virtually no and synchronous digital hierarchy (SDH) to optical disturbance on output phase transport network (OTN) mapping/demapping Supports Telcordia GR-253 jitter generation, transfer, and Cleanup of reference clock jitter tolerance for SONET/SDH up to OC-192 systems SONET/SDH clocks up to OC-192, including FEC Supports ITU-T G.8262 synchronous Ethernet slave clocks Stratum 3 holdover, jitter cleanup, and phase transient Supports ITU-T G.823, ITU-T G.824, ITU-T G.825, and control ITU-T G.8261 Cable infrastructure Auto/manual holdover and reference switchover Data communications Adaptive clocking allows dynamic adjustment of feedback Professional video dividers for use in OTN mapping/demapping applications GENERAL DESCRIPTION Quad digital phase-locked loop (DPLL) architecture with four The AD9554-1 is a low loop bandwidth clock translator that reference inputs (single-ended or differential) provides jitter cleanup and synchronization for many systems, 4 4 crosspoint allows any reference input to drive any PLL including synchronous optical networks (SONET/SDH). The Input reference frequencies from 2 kHz to 1000 MHz AD9554-1 generates an output clock synchronized to up to four Reference validation and frequency monitoring: 2 ppm external input references. The digital PLLs (DPLLs) allow Programmable input reference switchover priority reduction of input time jitter or phase noise associated with the 20-bit programmable input reference divider external references. The digitally controlled loop and holdover 4 differential clock outputs with each differential pair circuitry of the AD9554-1 continuously generates a low jitter configurable as HCSL, LVDS-compatible, or LVPECL- output clock even when all reference inputs have failed. compatible Output frequency range: 430 kHz to 941 MHz The AD9554-1 operates over an industrial temperature range of Programmable 18-bit integer and 24-bit fractional feedback 40C to +85C. The AD9554 is a version of this device with divider in digital PLL two outputs per PLL. If a single or dual DPLL version of this Programmable loop bandwidths from 0.1 Hz to 4 kHz device is needed, refer to the AD9557 or AD9559, respectively. 56-lead (8 mm 8 mm) LFCSP package FUNCTIONAL BLOCK DIAGRAM SERIAL INTERFACE STATUS AND 2 CONTROL PINS (SPI OR I C) 3 TO 11 DIGITAL ANALOG Q0 B DIVIDER P0 DIVIDER PLL0 PLL0 DIGITAL ANALOG 3 TO 11 Q1 B DIVIDER REFERENCE PLL1 PLL1 P1 DIVIDER INPUT MONITOR AND MUX DIGITAL ANALOG 3 TO 11 Q2 B DIVIDER PLL2 PLL2 P2 DIVIDER DIGITAL ANALOG 3 TO 11 Q3 B DIVIDER PLL3 PLL3 P3 DIVIDER STABLE CLOCK SOURCE MULTIPLIER AD9554-1 Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 12214-001AD9554-1 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Digital PLL (DPLL) Core .......................................................... 33 Applications ....................................................................................... 1 Loop Control State Machine ..................................................... 36 General Description ......................................................................... 1 System Clock (SYSCLK) ................................................................ 37 Functional Block Diagram .............................................................. 1 SYSCLK Inputs ........................................................................... 37 Revision History ............................................................................... 4 SYSCLK Multiplier ..................................................................... 37 Specif icat ions ..................................................................................... 5 Output Analog PLL (APLL) .......................................................... 39 Supply Voltage ............................................................................... 5 APLL Configuration .................................................................. 39 Supply Current .............................................................................. 5 APLL Calibration ....................................................................... 39 Power Dissipation ......................................................................... 6 Clock Distribution .......................................................................... 40 System Clock Inputs (XOA, XOB) ............................................. 6 Clock Dividers ............................................................................ 40 Reference Inputs ........................................................................... 7 Output Amplitude and Power-Down ...................................... 40 Reference Monitors ...................................................................... 8 Clock Distribution Synchronization ........................................ 41 Reference Switchover Specifications .......................................... 8 Status and Control .......................................................................... 42 Distribution Clock Outputs ........................................................ 9 Multifunction Pins (M0 to M3 and M5 to M7) ......................... 42 Time Duration of Digital Functions ........................................ 11 IRQ Function .............................................................................. 42 Digital PLL (DPLL 0, DPLL 1, DPLL 2, and DPLL 3) ...... 11 Watchdog Timer ......................................................................... 43 Analog PLL (APLL 0, APLL 1, APLL 2, and APLL 3) ...... 11 Serial Control Port ......................................................................... 44 Digital PLL Lock Detection ...................................................... 12 SPI/I2C Port Selection ................................................................ 44 Holdover Specifications ............................................................. 12 SPI Serial Port Operation .......................................................... 44 Serial Port SpecificationsSerial Port Interface (SPI) Mode .... 12 I2C Serial Port Operation .......................................................... 47 2 Serial Port SpecificationsI C Mode ...................................... 13 Programming the I/O Registers ................................................... 50 RESET Buffered/Active Registers .......................................................... 50 Logic Inputs ( , M0 to M3, M5 to M7) ......................... 14 Write Detect Registers ............................................................... 50 Logic Outputs (M0 to M3 and M5 to M7) .............................. 14 Autoclear Registers ..................................................................... 50 Jitter Generation ......................................................................... 14 Register Access Restrictions ...................................................... 50 Absolute Maximum Ratings .......................................................... 16 Thermal Performance .................................................................... 51 ESD Caution ................................................................................ 16 Power Supply Partitions ................................................................. 52 Pin Configuration and Function Descriptions ........................... 17 VDD Supplies ............................................................................. 52 Typical Performance Characteristics ........................................... 20 VDD SP Supply ......................................................................... 52 Input/Output Termination Recommendations .......................... 23 Register Map ................................................................................... 53 Getting Started ................................................................................ 24 Register Map Bit Descriptions ...................................................... 63 Chip Power Monitor and Startup ............................................. 24 Serial Control Port Configuration (Register 0x0000 to Multifunction Pins at Reset/Power-Up ................................... 24 Register 0x0001) ......................................................................... 63 Device Register Programming Using a Register Setup File ....... 24 Clock Part Family ID (Register 0x0003 to Register 0x0006) ..... 63 Register Programming Overview ............................................. 28 SPI Version (Register 0x000B) .................................................. 64 Theory of Operation ...................................................................... 31 Vendor ID (Register 0x000C to Register 0x000D) ................ 64 O ver vie w ...................................................................................... 31 IO Update (Register 0x000F) ................................................... 64 Reference Input Physical Connections .................................... 32 General Configuration (Register 0x0100 to Register 0x010E) .. 64 Reference Monitors .................................................................... 32 IRQ Mask (Register 0x010F to Register 0x011F) ................... 65 Reference Input Block ................................................................ 32 System Clock (Register 0x0200 to Register 0x0208) ............. 67 Reference Switchover ................................................................. 33 Rev. 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