Quad Input Multiservice Line Card Adaptive Clock Translator with Frame Sync Data Sheet AD9558 FEATURES Pin program function for easy frequency translation configuration Supports GR-1244 Stratum 3 stability in holdover mode Software controlled power-down Supports smooth reference switchover with virtually 64-lead, 9 mm 9 mm, LFCSP package no disturbance on output phase Supports Telcordia GR-253 jitter generation, transfer, and APPLICATIONS tolerance for SONET/SDH up to OC-192 systems Network synchronization, including synchronous Ethernet Supports ITU-T G.8262 synchronous Ethernet slave clocks and SDH to OTN mapping/demapping Supports ITU-T G.823, G.824, G.825, and G.8261 Cleanup of reference clock jitter Auto/manual holdover and reference switchover SONET/SDH/OTN clocks up to 100 Gbps, including FEC 4 reference inputs (single-ended or differential) Stratum 3 holdover, jitter cleanup, and phase transient control Input reference frequencies: 2 kHz to 1250 MHz Wireless base station controllers Reference validation and frequency monitoring (1 ppm) Cable infrastructure Programmable input reference switchover priority Data communications 20-bit programmable input reference divider 6 pairs of clock output pins with each pair configurable as GENERAL DESCRIPTION a single differential LVDS/HSTL output or as 2 single-ended The AD9558 is a low loop bandwidth clock multiplier that provides CMOS outputs jitter cleanup and synchronization for many systems, including Output frequencies: 352 Hz to 1250 MHz synchronous optical networks (OTN/SONET/SDH). The AD9558 Programmable 17-bit integer and 23-bit fractional generates an output clock synchronized to up to four external input feedback divider in digital PLL references. The digital phase-locked loop (PLL) allows reduction Programmable digital loop filter covering loop bandwidths of input time jitter or phase noise associated with the external from 0.1 Hz to 5 kHz (2 kHz maximum for <0.1 dB of peaking) references. The digitally controlled loop and holdover circuitry Low noise system clock multiplier of the AD9558 continuously generates a low jitter output clock Frame sync support even when all reference inputs have failed. Adaptive clocking The AD9558 operates over an industrial temperature range of Optional crystal resonator for system clock input 40C to +85C. If a smaller package is required, refer to the On-chip EEPROM to store multiple power-up profiles AD9557 for the two-input/two-output version of the same device. FUNCTIONAL BLOCK DIAGRAM STABLE SOURCE AD9558 CHANNEL 0 DIVIDER CLOCK MULTIPLIER CHANNEL 1 DIVIDER 3 TO 11 HF DIVIDER 0 DIGITAL ANALOG PLL PLL CHANNEL 2 3 TO 11 REFERENCE INPUT DIVIDER HF DIVIDER 1 AND MONITOR MUX CHANNEL 3 FRAME SYNC DIVIDER SERIAL INTERFACE STATUS AND EEPROM 2 (SPI OR I C) CONTROL PINS Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 09758-001AD9558 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Loop Control State Machine ..................................................... 36 Applications ....................................................................................... 1 System Clock (SYSCLK) ................................................................ 37 General Description ......................................................................... 1 System Clock Inputs................................................................... 37 Functional Block Diagram .............................................................. 1 System Clock Multiplier ............................................................ 37 Revision History ............................................................................... 3 Output PLL (APLL) ....................................................................... 39 Specifications ..................................................................................... 5 Clock Distribution .......................................................................... 40 Supply Voltage ............................................................................... 5 RF Dividers (RF Divider 2 and RF Divider 1) ........................ 40 Supply Current .............................................................................. 5 Channel Dividers ........................................................................ 40 Power Dissipation ......................................................................... 6 Output Power-Down ................................................................. 40 Logic Inputs (SYNC, RESET, PINCONTROL, M7 to M0) ....... 6 Output Enable ............................................................................. 40 Output Mode .............................................................................. 40 Logic Outputs (M7 to M0, IRQ) ................................................ 7 Clock Distribution Synchronization ........................................ 41 System Clock Inputs (XOA, XOB) ............................................. 7 Frame Synchronization .................................................................. 42 Reference Inputs ........................................................................... 8 Reference Configuration in Frame Synchronization Mode .... 42 Reference Monitors ...................................................................... 9 Clock Outputs in Frame Synchronization Mode ................... 42 Reference Switchover Specifications .......................................... 9 Control Registers for Frame Synchronization Mode............. 42 Distribution Clock Outputs ...................................................... 10 Level Sensitive Mode and One-Shot Mode ............................. 42 Time Duration of Digital Functions ........................................ 11 M3b Divider/OUT5 Programming in Frame Synchronization Digital PLL .................................................................................. 12 Mode ............................................................................................ 43 Digital PLL Lock Detection ...................................................... 12 Status and Control .......................................................................... 44 Holdover Specifications ............................................................. 12 Multifunction Pins (M7 to M0) ............................................... 44 Serial Port SpecificationsSPI Mode ...................................... 13 Watchdog Timer ......................................................................... 45 2 Serial Port SpecificationsI C Mode ...................................... 14 EEPROM ..................................................................................... 45 Jitter Generation ......................................................................... 14 Serial Control Port ......................................................................... 51 Absolute Maximum Ratings .......................................................... 17 SPI/IC Port Selection ................................................................ 51 ESD Caution ................................................................................ 17 SPI Serial Port Operation .......................................................... 51 Pin Configuration and Function Descriptions ........................... 18 IC Serial Port Operation .......................................................... 55 Typical Performance Characteristics ........................................... 21 Programming the I/O Registers ................................................... 58 Input/Output Termination Recommendations .......................... 26 Buffered/Active Registers .......................................................... 58 Getting Started ................................................................................ 27 Autoclear Registers ..................................................................... 58 Chip Power Monitor and Startup ............................................. 27 Register Access Restrictions...................................................... 58 Multifunction Pins at Reset/Power-Up ................................... 27 Thermal Performance .................................................................... 59 Device Register Programming Using a Register Setup File ..... 27 Power Supply Partitions ................................................................. 60 Register Programming Overview ............................................. 28 Recommended Configuration for 3.3 V Switching Supply ..... 60 Theory of Operation ...................................................................... 31 Configuration for 1.8 V Supply ................................................ 60 Overview ...................................................................................... 31 Pin Program Function Description ............................................. 61 Reference Clock Inputs .............................................................. 32 Overview of On-Chip ROM Features ..................................... 61 Reference Monitors .................................................................... 32 Hard Pin Programming Mode.................................................. 62 Reference Profiles ....................................................................... 32 Soft Pin Programming Overview ............................................. 63 Reference Switchover ................................................................. 32 Register Map ................................................................................... 64 Digital PLL (DPLL) Core .......................................................... 33 Rev. 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