PCI-Express Clock Generator IC, PLL Core, Dividers, Two Outputs AD9573 FEATURES GENERAL DESCRIPTION Fully integrated VCO/PLL core The AD9573 provides a highly integrated, dual output clock 0.54 ps rms jitter from 12 kHz to 20 MHz generator function including an on-chip PLL core that is Input crystal frequency of 25 MHz optimized for PCI-e applications. The integer-N PLL design Preset divide ratios for 100 MHz, 33.33 MHz is based on the Analog Devices, Inc., proven portfolio of high LVDS/LVCMOS output format performance, low jitter frequency synthesizers to maximize line Integrated loop filter card performance. Other applications with demanding phase Space saving 4.4 mm 5.0 mm TSSOP noise and jitter requirements also benefit from this part. 0.235 W power dissipation The PLL section consists of a low noise phase frequency 3.3 V operation detector (PFD), a precision charge pump, a low phase noise voltage controlled oscillator (VCO), and a preprogrammed APPLICATIONS feedback divider and output divider. Line cards, switches, and routers CPU/PCIe applications By connecting an external 25 MHz crystal, output frequencies Low jitter, low phase noise clock generation of 100 MHz and 33.33 MHz can be locked to the input reference. The output divider and feedback divider ratios are prepro- grammed for the required output rates. No external loop filter components are required, thus conserving valuable design time and board space. The AD9573 is available in a 16-lead 4.4 mm 5.0 mm TSSOP and can be operated from a single 3.3 V supply. The temperature range is 40C to +85C. FUNCTIONAL BLOCK DIAGRAM VDD 5 LDO LVDS 100MHz VCO XTAL OSC LVCMOS 33.33MHz AD9573 GND 5 OE Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PFD/CP 3RD ORDER LPF DIVIDERS 07500-001AD9573 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................5 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions ..............................6 General Description ......................................................................... 1 Typical Performance Characteristics ..............................................7 Functional Block Diagram .............................................................. 1 Terminology .......................................................................................8 Revision History ............................................................................... 2 Theory of Operation .........................................................................9 Specif icat ions ..................................................................................... 3 Outputs ...........................................................................................9 PLL Characteristics ...................................................................... 3 Phase Frequency Detector (PFD) and Charge Pump ..........9 Clock Output Jitter ....................................................................... 3 Power Supply ..................................................................................9 Clock Outputs ............................................................................... 3 LVDS Clock Distribution .......................................................... 10 Timing Characteristics ................................................................ 4 CMOS Clock Distribution ........................................................ 10 Control Pins .................................................................................. 4 Power and Grounding Considerations and Power Supply Rejection ...................................................................................... 10 Power .............................................................................................. 4 Outline Dimensions ....................................................................... 11 Crystal Oscillator .......................................................................... 4 Ordering Guide .......................................................................... 11 Timing Diagrams .......................................................................... 4 Absolute Maximum Ratings ............................................................ 5 Thermal Resistance ...................................................................... 5 REVISION HISTORY 7/09Revision 0: Initial Version Rev. 0 Page 2 of 12