Ethernet/Gigabit Ethernet Clock Generator Data Sheet AD9574 FEATURES FUNCTIONAL BLOCK DIAGRAM Redundant input reference clock capability REF0 P OUT0 P Rx 1/2 Reference monitoring function AD9574 OUT0 N REF0 N REF1 P Fully integrated VCO/PLL core OUT1 P Rx REF1 N OUT1 N Jitter (rms) 0.234 ps rms jitter (10 kHz to 10 MHz) at 156.25 MHz OUT2 P OUT2 N REF SEL 0.243 ps rms jitter (12 kHz to 20 MHz) at 156.25 MHz OUT3 P Input frequency: 19.44 MHz or 25 MHz OUT3 N OUT4 P Preset frequency translations MCLK x OUT4 N Using a 19.44 MHz input reference REF ACT OUT5 P OUT5 N 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz REF SW REF FLO OUT6 P Using a 25 MHz input reference PFD/ REF FHI LF VCO OUT6 N CP 1/2 25 MHz, 33.33 MHz, 50 MHz, 66.67 MHz, 80 MHz, REFMON PPR 100 MHz, 125 MHz, 133.3 MHz, 156.25 MHz, 160 MHz, PPRx CONTROL 312.5 MHz LD LF Output drive formats: HSTL, LVDS, HCSL, and 1.8 V and 3.3 V Figure 1. CMOS Integrated loop filter (requires a single external capacitor) 2 copies of reference clock output Device configuration via strapping pins (PPRx) Space-saving 7 mm 7 mm 48-lead LFCSP 3.3 V operation APPLICATIONS Ethernet line cards, switches, and routers SATA and PCI express Low jitter, low phase noise clock generation GENERAL DESCRIPTION The AD9574 provides a multiple output clock generator function clock source (8 kHz/10 MHz/19.44 MHz/25 MHz/38.88 MHz) to comprising a dedicated phase-locked loop (PLL) core optimized the monitor clock input enables the optional monitor circuit for Ethernet and gigabit Ethernet line card applications. The providing quality of service (QoS) status for REF0 or REF1. integer-N PLL design is based on the Analog Devices, Inc., The PLL section consists of a low noise phase frequency proven portfolio of high performance, low jitter frequency detector (PFD), a precision charge pump (CP), a partially synthesizers to maximize network performance. The AD9574 integrated loop filter (LF), a low phase noise voltage controlled also benefits other applications requiring low phase noise and oscillator (VCO), and feedback and output dividers. The divider jitter performance. values depend on the PPRx pins. The integrated loop filter Configuring the AD9574 for a particular application requires requires only a single external capacitor connected to the LF pin. only the connection of external pull-up or pull-down resistors The AD9574 is packaged in a 48-lead 7 mm 7 mm LFCSP, to the appropriate pin program reader pins (PPRx). These pins requiring only a single 3.3 V supply. The operating temperature provide control of the internal dividers for establishing the range is 40C to +85C. desired frequency translations, clock output functionality, and Note that throughout this data sheet, OUT0 to OUT6, REF0, input reference functionality. Connecting an external 19.44 MHz and REF1 refer to the respective channels, which consist of the or 25 MHz oscillator to one or both of the REF0 P/REF0 N or differential pins, OUT0 P/OUT0 N to OUT6 P/OUT6 N, REF1 P/REF1 N reference inputs results in a set of output REF0 P/REF0 N, and REF1 P/REF1 N, respectively. frequencies prescribed by the PPRx pins. Connecting a stable Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20142017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com REFERENCE SWITCH REFERENCE MONITOR DIVIDERS 07501-001AD9574 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Overview ..................................................................................... 21 Applications ....................................................................................... 1 PPRx Pins .................................................................................... 21 Functional Block Diagram .............................................................. 1 PPR0Reference Clock Input Configuration ................... 22 General Description ......................................................................... 1 PPR1Frequency Translation Settings .............................. 22 Revision History ............................................................................... 2 PPR2OUT0 and OUT1 Configuration ........................... 23 Specifications ..................................................................................... 3 PPR3OUT4 and OUT5 Configuration ........................... 23 OUT0 Channel Absolute Clock Jitter ........................................ 3 PPR4OUT6 Configuration ............................................... 24 OUT1 Channel Absolute Clock Jitter ........................................ 3 PPR5Reference Monitor Threshold ................................. 24 OUT2 and OUT3 Channels Absolute Clock Jitter................... 3 PPR6Monitor Clock (MCLK x) Input Configuration . 24 OUT4 and OUT5 Channels Absolute Clock Jitter................... 4 Dependency of PPR3 and PPR4 on PPR1 .......................... 24 OUT6 Channel Absolute Clock Jitter ........................................ 5 Power-On Reset (POR) ............................................................. 25 Clock Outputs (OUT0 x to OUT6 x)Static ........................ 6 Reference Clock Inputs .............................................................. 27 Clock Outputs (OUT0 x to OUT6 x)Dynamic .................. 6 Monitor Clock Input .................................................................. 27 Monitor Clock Inputs (MCLK x)Static ................................ 7 Reference Switching ................................................................... 27 Monitor Clock Inputs (MCLK x)Dynamic .......................... 8 Reference Monitor ...................................................................... 27 Reference Inputs (REF0 x and REF1 x)Static ..................... 8 PLL ............................................................................................... 28 Reference Inputs (REF0 x and REF1 x)Dynamic .............. 8 Output Drivers ............................................................................ 29 Reference Switchover Output Disturbance ............................... 9 Output Clocks ............................................................................. 29 Control Pins .................................................................................. 9 Applications Information .............................................................. 30 Status Pins .................................................................................... 10 Dual Oscillator Reference Input Application ......................... 30 Power Supply and Dissipation .................................................. 10 Simple, Single Oscillator Reference Input Application ......... 31 Timing Specifications ................................................................ 11 Interfacing to CMOS Clock Outputs ....................................... 31 Timing Diagrams ........................................................................ 12 Interfacing to LVDS and HSTL Clock Outputs ..................... 32 Absolute Maximum Ratings .......................................................... 13 Interfacing to HCSL Clock Outputs ........................................ 32 ESD Caution ................................................................................ 13 Power Supply ............................................................................... 33 Pin Configuration and Function Descriptions ........................... 14 Power and Grounding Considerations and Power Supply Rejection ...................................................................................... 33 Typical Performance Characteristics ........................................... 17 Thermal Performance .................................................................... 34 Phase Noise and Voltage Waveforms ....................................... 17 Outline Dimensions ....................................................................... 35 Reference Switching Frequency and Phase Disturbance ...... 19 Ordering Guide .......................................................................... 35 Terminology .................................................................................... 20 Theory of Operation ...................................................................... 21 REVISION HISTORY 4/2017Rev. A to Rev. B Deleted Thermal Resistance Section and Table 18 Renumbered Change to Figure 20 ....................................................................... 21 Sequentially ..................................................................................... 13 Updated Outline Dimensions ....................................................... 35 Changes to Power-On Reset (POR) Section ............................... 26 Changes to Ordering Guide .......................................................... 35 Added Figure 22 Renumbered Sequentially .............................. 26 Added Thermal Performance Section and Table 35 .................. 34 1/2015Rev. 0 to Rev. A Changes to Table 13 .......................................................................... 9 9/2014Revision 0: Initial Version Changes to Note 1, Table 17 .......................................................... 13 Rev. B Page 2 of 35