Network Clock Generator, Two Outputs AD9575 FEATURES GENERAL DESCRIPTION Fully integrated VCO/PLL core The AD9575 provides a highly integrated, dual output clock 0.39 ps rms jitter from 12 kHz to 20 MHz at 156.25 MHz generator function including an on-chip PLL core that is 0.15 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz optimized for network clocking. The integer-N PLL design is 0.40 ps rms jitter from 12 kHz to 20 MHz at 106.25 MHz based on the Analog Devices, Inc., proven portfolio of high 0.15 ps rms jitter from 637 kHz to 10 MHz at 106.25 MHz performance, low jitter frequency synthesizers to maximize line Input crystal frequency of 19.44 MHz, 25 MHz, or card performance. Other applications with demanding phase 25.78125 MHz noise and jitter requirements also benefit from this part. Pin selectable divide ratios for 33.33 MHz, 62.5 MHz, The PLL section consists of a low noise phase frequency detector 100 MHz, 106.25 MHz, 125 MHz, 155.52 MHz, 156.25 MHz, (PFD), a precision charge pump (CP), a low phase noise voltage 159.375 MHz, 161.13 MHz, and 312.5 MHz outputs controlled oscillator (VCO), and pin selectable feedback and LVDS/LVPECL/LVCMOS output format output dividers. Integrated loop filter By connecting an external crystal, popular network output fre- Space saving 4.4 mm 5.0 mm TSSOP quencies can be locked to the input reference. The output divider 100 mA power supply current (LVDS output) and feedback divider ratios are pin programmable for the required 120 mA power supply current (LVPECL output) output rates. No external loop filter components are required, 3.3 V operation thus conserving valuable design time and board space. APPLICATIONS The AD9575 is available in a 16-lead, 4.4 mm 5.0 mm TSSOP GbE/FC/SONET line cards, switches, and routers and can be operated from a single 3.3 V supply. The temperature CPU/PCI-E applications range is 40C to +85C. Low jitter, low phase noise clock generation FUNCTIONAL BLOCK DIAGRAM VDD 5 LVDS OR LDO LVPECL 100MHz TO 312.5MHz VCO XTAL OSC LVCMOS 33.33MHz/ 62.5MHz/SEL1 SEL AD9575 GND 5 SEL0 Figure 1. Rev.Rev. A A IInnffoormarmattioionn furnfurniishsheedd b byy A Annaalloogg D Deevviicceess isis be belliieevveded ttoo bebe a accccuurraattee an andd r reelliiaabblele. H. Hoowweevveerr,, n noo rresespponsonsiibbiilliittyy i iss aassussumed bmed byy AAnnaallog og DeDevviiccees fs foor itr its uses use,, nor fnor foor anr anyy inf infrinringegemenmentts s ooff ppaattenentts s oor r oottheherr OOne Tne Teechnology chnology Way,Way, P P..O.O. B Boox 91x 9106,06, Nor Norwwoodood,, MA 020 MA 02062-62-9109106,6, U. U.SS..A.A. rriigghhts ots off ththirirdd parparttiesies th thaatt m maayy r reesusulltt f frroomm iitts s useuse.. S Sppeecicifficaicattioionnss su subjbjeecct tt too c chhananggee w wiiththoouut nt nootiticcee NNoo TTeel:l: 781. 781.329.329.44700700 wwwwww..analoganalog.c.comom lliicceennssee i iss g grranantteedd bbyy impimpllicicaattioionn o orr o otthheerrwwiisse e ununddeer anr anyy papatteenntt o orr pa patteenntt r riigghhttss o off A Annaalloogg D Deevviicceess.. Fax:Fax: 781. 781.461.461.31311313 2010 A2010 Analog Denalog Devices,vices, I Inc.nc. Al All rl rightights rs reeserservedved TTrrademademararksks and and r regegiiststeerreded trtradademaemarksrks ar aree thethe p prrooppererttyy of of thetheiirr r reespspeeccttiivvee o ownewnersrs PFD/CP THIRD-ORDER LPF DIVIDERS 08462-001AD9575 TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................7 Applications ....................................................................................... 1 Thermal Resistance .......................................................................7 General Description ......................................................................... 1 ESD Caution...................................................................................7 Functional Block Diagram .............................................................. 1 Pin Configuration and Function Descriptions ..............................8 Revision History ............................................................................... 2 Typical Performance Characteristics ..............................................9 Specif icat ions ..................................................................................... 3 Terminology .................................................................................... 11 PLL Characteristics ...................................................................... 3 Theory of Operation ...................................................................... 12 LVDS Clock Output Jitter (Typ/Max) ........................................ 4 Phase Frequency Detector (PFD) and Charge Pump ............ 12 LVPECL Clock Output Jitter (Typ/Max) ................................... 4 Power Supply ............................................................................... 12 Output Frequency Select ............................................................. 5 LVPECL Clock Distribution ..................................................... 12 Clock Outputs ............................................................................... 5 LVDS Clock Distribution .......................................................... 13 Timing Characteristics ................................................................ 5 LVCMOS Clock Distribution ................................................... 13 Power .............................................................................................. 6 Typical Application Circuit ....................................................... 13 Crystal Oscillator .......................................................................... 6 Outline Dimensions ....................................................................... 14 Timing Diagrams .......................................................................... 6 Ordering Guide .......................................................................... 14 REVISION HISTORY 3/10Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Changes to Table 1, Table 2, and Table 3 ....................................... 4 Changes to Table 4 and Table 6 ....................................................... 5 Changes to Table 7 and Table 8 ....................................................... 6 Changes to Table 12 .......................................................................... 8 Added Figure 11 Renumbered Figures Sequentially ................ 10 Changes to Figure 13 ...................................................................... 10 Changes to Theory of Operation Section and Figure 19 ........... 12 Changes to Figure 24 ...................................................................... 13 1/10Revision 0: Initial Version Rev. A Page 2 of 16