Dual PLL, Asynchronous Clock Generator Data Sheet AD9576 FEATURES FUNCTIONAL BLOCK DIAGRAM Single, low phase noise, fully integrated VCO/fractional-N PLL core 2 SPI/I C STATUS AND PPRx MONITOR VCO range: 2375 MHz to 2725 MHz OPTIONAL CONTROL REF2 Integrated loop filter (requires a single external capacitor) DIV GENERAL- OUT10 2 differential, XTAL, or single-ended reference inputs REF2 PURPOSE PLL OUT9 Reference monitoring capability DIV OUT8 Automatic redundant XTAL switchover OUT0 Minimal transient, smooth switching OUT1 DIV OPTIONAL OUT2 Typical RMS jitter REF0 OUT3 <0.3 ps (12 kHz to 20 MHz), integer-N translations REF0 VCO OUT4 <0.5 ps (12 kHz to 20 MHz), fractional-N translations DIV DIV OUT5 OPTIONAL Input frequency REF1 OUT6 VCO DIV 8 kHz, 1.544 MHz, 2.048 MHz, and 10 MHz to 325 MHz OUT7 DIV REF1 Preset frequency translations via pin strapping (PPRx) AD9576 Using a 25 MHz input reference 24.576 MHz, 25 MHz, 33.33 MHz, 50 MHz, 70.656 MHz, Figure 1. 100 MHz, 125 MHz, 148.5 MHz, 156.25 MHz, GENERAL DESCRIPTION 161.1328 MHz, 312.5 MHz, 322.2656 MHz, 625 MHz, The AD9576 provides a multiple output clock generator or 644.5313 MHz Using a 19.44 MHz input reference function comprising two dedicated phase-locked loop (PLL) 50 MHz, 100 MHz, 125 MHz, 156.25 MHz, 161.1328 MHz, cores with flexible frequency translation capability, optimized to or 644.5313 MHz serve as a robust source of asynchronous clocks for an entire Using a 30.72 MHz input reference system, providing extended operating life within frequency 25 MHz, 50 MHz, 100 MHz, 125 MHz, or 156.25 MHz tolerance through monitoring of and automatic switchover Single, general-purpose, fully integrated VCO/integer-N between redundant crystal (XTAL) inputs with minimized PLL core switching, induced transients. The fractional-N PLL design is VCO range: 750 MHz to 825 MHz based on the Analog Devices, Inc., proven portfolio of high Integrated loop filter performance, low jitter frequency synthesizers to maximize Independent, duplicate reference input or operation from network performance, whereas the integer-N PLL provides the fractional-N PLL active reference input general-purpose clocks for use as CPU and field-programmable Input frequency: 25 MHz gate array (FPGA) reference clocks. Preset frequency translations via pin strapping (PPRx) The AD9576 uses pin strapping to select among a multitude of 25 MHz, 33.33 MHz, 50 MHz, 66.67 MHz, 100 MHz, power-on ready configurations for its 11 output clocks, which 133.33 MHz, 200 MHz, or 400 MHz require only the connection of external pull-up or pull-down Up to 3 copies of reference clock output resistors to the appropriate pin program reader pins (PPRx). 11 pairs of configurable differential outputs These pins provide control of the internal dividers for establishing Output drive formats the desired frequency translations, clock output functionality, 3 outputs: HSTL, LVDS, HCSL, 1.8 V CMOS, 2.5 V/3.3 V CMOS and input reference functionality. These parameters can also be 8 outputs: HSTL, LVDS, or 1.8 V CMOS manually configured through a serial port interface (SPI). 2.5 V or 3.3 V single-supply operation The AD9576 is packaged in a 64-lead, 9 mm 9 mm LFCSP, APPLICATIONS requiring only a single 2.5 V or 3.3 V supply. The operating Ethernet line cards, switches, and routers temperature range is 40C to +85C. Baseband units Each OUTx output is differential and contains two pins: OUTx SATA and PCI express and OUTx. For simplicity, the term OUTx refers to the Low jitter, low phase noise clock generation functional output block containing these two pins. Asynchronous clock generation Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20162018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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SWITCHOVER MUX AND MONITOR FRACTIONAL-N PLL 13993-001AD9576 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 PLL0 Integer-N/Fractional-N PLL ........................................... 29 Applications ....................................................................................... 1 PLL1 Integer-N PLL ................................................................... 35 Functional Block Diagram .............................................................. 1 Output Distribution ................................................................... 36 General Description ......................................................................... 1 PPRx Pins .................................................................................... 38 Revision History ............................................................................... 3 Power-On Reset (POR) ............................................................. 41 Specifications ..................................................................................... 4 Serial Control Port ......................................................................... 42 Conditions ..................................................................................... 4 SPI/IC Port Selection ................................................................ 42 Supply Current Specifications ..................................................... 4 SPI Serial Port Operation .......................................................... 42 2 Power Dissipation Specifications ............................................... 5 I C Serial Port Operation .......................................................... 44 Reference Inputs ........................................................................... 6 Control Register Map ..................................................................... 48 Reference Switchover Output Disturbance Specifications...... 6 Control Register Descriptions ...................................................... 51 PLL0 Characteristics .................................................................... 7 Serial Port Configuration Registers (Register 0x000 to Register 0x00F) ........................................................................... 51 PLL1 Characteristics .................................................................... 7 Status Indicator Registers (Register 0x020 to Register 0x021) .. 52 Clock Distribution Outputs Specifications ............................... 7 Chip Mode Register (Register 0x040) ..................................... 52 Output Alignment and Startup Specifications ....................... 10 Reference Input Configuration Registers (Register 0x080 to PLL0 Channels Absolute Clock Jitter Specifications ............. 11 Register 0x081) ........................................................................... 53 PLL1 and Bypass Channel Absolute Clock Jitter Reference Switchover Registers (Register 0x082 to Specifications .............................................................................. 13 Register 0x083) ........................................................................... 54 OUT8 to OUT10 Channel Cycle to Cycle Clock Jitter PLL0 Configuration Registers (Register 0x100 to Specifications .............................................................................. 13 Register 0x111) ........................................................................... 55 RESET Logic Input Pins CharacteristicsREF SEL, , SPx, PLL0 VCO Dividers Registers (Register 0x120 to PPRx ............................................................................................. 14 Register 0x122) ........................................................................... 57 Status Output Pins CharacteristicsLD 0, LD 1, REF SW, PLL0 Distribution Registers (Register 0x140 to REF STATUS, REF ACT ......................................................... 14 Register 0x14D) .......................................................................... 58 Serial Control Port Specifications ............................................ 15 PLL1 Configuration Registers (Register 0x200 to Absolute Maximum Ratings .......................................................... 17 Register 0x202) ........................................................................... 60 Thermal Resistance .................................................................... 17 PLL1 Distribution Registers (Register 0x240 to Register 0x246) ........................................................................... 60 ESD Caution ................................................................................ 17 Applications Information .............................................................. 63 Pin Configuration and Function Descriptions ........................... 18 Interfacing to CMOS Clock Outputs ....................................... 63 Typical Performance Characteristics ........................................... 22 Phase Noise and Voltage Waveforms ....................................... 22 Interfacing to LVDS and HSTL Clock Outputs ..................... 63 Interfacing to HCSL Clock Outputs ........................................ 63 Reference Switching Frequency and Phase Disturbance ...... 24 Power Supply ............................................................................... 64 Terminology .................................................................................... 25 Power and Grounding Considerations and Power Supply Theory of Operation ...................................................................... 26 Rejection ...................................................................................... 64 Overview ...................................................................................... 26 Outline Dimensions ....................................................................... 65 Reference Inputs ......................................................................... 26 Ordering Guide .......................................................................... 65 Reference Monitor ...................................................................... 27 Reference Switching ................................................................... 28 Rev. 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