Clock Generator with Dual PLLs, Spread Spectrum, and Margining Data Sheet AD9577 FEATURES FUNCTIONAL BLOCK DIAGRAM REFSEL Fully integrated dual PLL/VCO cores 1 integer-N and 1 fractional-N PLL XT1 XTAL CMOS OSC Continuous frequency coverage from 11.2 MHz to 200 MHz XT2 REFOUT Most frequencies from 200 MHz to 637.5 MHz available REFCLK PLL1 phase jitter (12 kHz to 20 MHz): 460 fs rms typical DIVIDE 1 OR 2 PLL2 phase jitter (12 kHz to 20 MHz) LDO PLL1 Integer-N mode: 470 fs rms typical Fractional-N mode: 660 fs rms typical VCO 2.15GHz LVPECL/LVDS Input crystal or reference clock frequency TO OR 2 CMOS 2.55GHz Optional reference frequency divide-by-2 2 I C programmable output frequencies FEEDBACK LVPECL/LVDS OR 2 CMOS Up to 4 LVDS/LVPECL or up to 8 LVCMOS output clocks DIVIDER 1 CMOS buffered reference clock output LDO PLL2 Spread spectrum: downspread 0, 0.5 % 2 pin-controlled frequency maps: margining VCO 2.15GHz LVPECL/LVDS Integrated loop filters TO OR 2 CMOS 2.55GHz Space saving, 6 mm 6 mm, 40-lead LFCSP package 1.02 W power dissipation (LVDS operation) FEEDBACK LVPECL/LVDS 1.235 W power dissipation (LVPECL operation) DIVIDER OR 2 CMOS 3.3 V operation SCL 2 I C SDA CONTROL MARGIN APPLICATIONS AD9577 SSCG SPREAD SPECTRUM, SDM MAX BW Low jitter, low phase noise multioutput clock generator for data communications applications including Ethernet, Figure 1. Fibre Channel, SONET, SDH, PCI-e, SATA, PTN, OTN, feedback divider, and two independently programmable output ADC/DAC, and digital video dividers. By connecting an external crystal or applying a reference Spread spectrum clocking clock to the REFCLK pin, frequencies of up to 637.5 MHz can be synchronized to the input reference. Each output divider and 2 feedback divider ratio is I C programmed for the required GENERAL DESCRIPTION output rates. The AD9577 provides a multioutput clock generator function, A second fractional-N PLL (PLL2) with a programmable modulus along with two on-chip phase-locked loop cores, PLL1 and PLL2, allows VCO frequencies that are fractional multiples of the optimized for network clocking applications. The PLL designs reference frequency to be synthesized. Each output divider are based on the Analog Devices, Inc., proven portfolio of high and feedback divider ratio can be programmed for the required performance, low jitter frequency synthesizers to maximize 2 output rates, up to 637.5 MHz. This fractional-N PLL can also network performance. The PLLs have I C programmable output operate in integer-N mode for the lowest jitter. frequencies and formats. The fractional-N PLL can support spread spectrum clocking for reduced EMI radiated peak power. Up to four differential output clock signals can be configured Both PLLs can support frequency margining. Other applications as either LVPECL or LVDS signaling formats. Alternatively, with demanding phase noise and jitter requirements can benefit the outputs can be configured for up to eight CMOS outputs. from this part. Combinations of these formats are supported. No external loop filter components are required, thus conserving valuable design The first integer-N PLL section (PLL1) consists of a low noise phase time and board space. The AD9577 is available in a 40-lead, 6 mm frequency detector (PFD), a precision charge pump (CP), a low 6 mm LFCSP package and can operate from a single 3.3 V supply. phase noise voltage controlled oscillator (VCO), a programmable The operating temperature range is 40C to +85C. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112016 Analog Devices, Inc. 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Technical Support www.analog.com f PFD PFD/CP PFD/CP THIRD THIRD ORDER LPF ORDER LPF DIVIDERS DIVIDERS DIVIDERS DIVIDERS 09284-001AD9577 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Example Application .................................................................. 28 Applications ....................................................................................... 1 Functional Description .................................................................. 29 General Description ......................................................................... 1 Reference Input and Reference Dividers ................................. 29 Functional Block Diagram .............................................................. 1 Output Channel Dividers .......................................................... 30 Revision History ............................................................................... 2 Outputs ........................................................................................ 30 Specifications ..................................................................................... 3 Reference Output Buffer ........................................................... 31 PLL1 Characteristics .................................................................... 3 PLL1 Integer-N PLL ................................................................... 31 PLL1 Clock Output Jitter ............................................................. 5 PLL1 Phase Frequency Detector (PFD) and Charge Pump . 32 PLL2 Fractional-N Mode Characteristics ................................. 6 PLL1 VCO ................................................................................... 32 PLL2 Integer-N Mode Characteristics ....................................... 7 PLL1 Feedback Divider ............................................................. 32 PLL2 Clock Output Jitter ............................................................. 9 Setting the Output Frequency of PLL1 .................................... 32 CMOS Reference Clock Output Jitter...................................... 11 PLL2 Integer/Fractional-N PLL ............................................... 32 Timing Characteristics .............................................................. 12 PLL2 Phase Frequency Detector (PFD) and Charge Pump . 33 Clock Outputs ............................................................................. 13 PLL2 Loop Bandwidth ............................................................... 33 Power ............................................................................................ 14 PLL2 VCO ................................................................................... 33 Crystal Oscillator ........................................................................ 15 PLL2 Feedback Divider ............................................................. 33 Reference Input ........................................................................... 15 PLL2 - Modulator ................................................................. 33 Control Pins ................................................................................ 15 Spur Mechanisms ....................................................................... 33 Absolute Maximum Ratings .......................................................... 16 Optimizing PLL Performance .................................................. 34 Thermal Characteristics ............................................................ 16 Setting the Output Frequency of PLL2 .................................... 34 ESD Caution ................................................................................ 16 Margining .................................................................................... 35 Pin Configuration and Function Descriptions ........................... 17 Spread Spectrum Clock Generation (SSCG) .......................... 35 2 Typical Performance Characteristics ........................................... 19 I C Interface Timing and Internal Register Description ........... 38 REFOUT and PLL1 Phase Noise Performance ...................... 19 Default Frequency Map and Output Formats ........................ 40 2 PLL2 Phase Noise Performance ................................................ 20 I C Interface Operation ............................................................. 40 Output Jitter ................................................................................ 21 Typical Application Circuits ..................................................... 42 Typical Output Signal ................................................................ 22 Power and Grounding Considerations and Power Supply Rejection ...................................................................................... 43 Typical Spread Spectrum Performance Characteristics ........ 24 Outline Dimensions ....................................................................... 44 Terminology .................................................................................... 25 Ordering Guide .......................................................................... 44 Detailed Block Diagram ................................................................ 27 REVISION HISTORY 8/2016Rev. 0 to Rev. A Changes to Outputs Section .......................................................... 30 10/2011Revision 0: Initial Version Rev. A Page 2 of 44