IF Digitizing Subsystem * AD9874 FEATURES GENERAL DESCRIPTION 10 MHz to 300 MHz Input Frequency The AD9874 is a general-purpose IF subsystem that digitizes a 7.2 kHz to 270 kHz Output Signal Bandwidth low level 10 MHz to 300 MHz IF input with a signal bandwidth 8.1 dB SSB NF ranging from 6.8 kHz to 270 kHz. The signal chain of the AD9874 0 dBm IIP3 consists of a low noise amplifier, a mixer, a band-pass sigma-delta AGC Free Range up to 34 dBm analog-to-digital converter, and a decimation filter with program- 12 dB Continuous AGC Range mable decimation factor. An automatic gain control (AGC) circuit 16 dB Front End Attenuator gives the AD9874 12 dB of continuous gain adjustment. Auxil- Baseband I/Q 16-Bit (or 24-Bit) Serial Digital Output iary blocks include both clock and LO synthesizers. LO and Sampling Clock Synthesizers The AD9874s high dynamic range and inherent antialiasing Programmable Decimation Factor, Output Format, provided by the band-pass sigma-delta converter allow the AGC, and Synthesizer Settings AD9874 to cope with blocking signals up to 95 dB stronger 370 Input Impedance than the desired signal. This attribute can often reduce the cost of 2.7 V to 3.6 V Supply Voltage a radio by reducing its IF filtering requirements. Also, it enables Low Current Consumption: 20 mA multimode radios of varying channel bandwidths, allowing the 48-Lead LQFP Package (1.4 mm Thick) IF filter to be specified for the largest channel bandwidth. APPLICATIONS The SPI port programs numerous parameters of the AD9874, Multimode Narrow-Band Radio Products thus allowing the device to be optimized for any given application. Analog/Digital UHF/VHF FDMA Receivers Programmable parameters include synthesizer divide ratios, AGC TETRA, APCO25, GSM/EDGE attenuation and attack/decay time, received signal strength level, Portable and Mobile Radio Products decimation factor, output data format, 16 dB attenuator, and the Base Station Applications selected bias currents. The bias currents of the LNA and mixer SATCOM Terminals can be further reduced at the expense of degraded performance for battery-powered applications. FUNCTIONAL BLOCK DIAGRAM MXOP MXON IF2P IF2N GCP GCN DAC AGC AD9874 16dB DECIMATION IFIN LNA - ADC FORMATTING/SSI DOUTA FILTER DOUTB FS CLKOUT FREF CONTROL LOGIC LO VOLTAGE CLK SYN SYN REFERENCE SPI IOUTL LOP LON IOUTC CLKP CLKN VREFP VCM VREFN PC PD PE SYNCB LO VCO AND LOOP FILTER LOOP FILTER *Protected by U.S. Patent No. 5,969,657 REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and Fax: 781/326-8703 2003 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective companies.AD9874 TABLE OF CONTENTS AD9874SPECIFICATIONS . 3 ABSOLUTE MAXIMUM RATINGS . 5 PIN CONFIGURATION/DESCRIPTION . 6 DEFINITION OF SPECIFICATIONS/ TEST METHODS 7 TYPICAL PERFORMANCE CHARACTERISTICS . 8 SERIAL PERIPHERAL INTERFACE (SPI) . 13 SYNCHRONOUS SERIAL INTERFACE (SSI) 16 Synchronization Using SYNCB 18 Interfacing to DSPs . 18 POWER CONTROL . 19 LO SYNTHESIZER 19 Fast Acquire Mode . 20 CLOCK SYNTHESIZER 21 IF LNA/MIXER . 22 BAND-PASS SIGMA DELTA ( - ) ADC 24 DECIMATION FILTER 26 VARIABLE GAIN AMPLIFIER WITH AGC 28 Variable Gain Control . 28 Automatic Gain Control . 29 System NF vs. VGA Control 31 APPLICATION CONSIDERATIONS . 32 Frequency Planning . 32 Spurious Responses . 33 EXTERNAL PASSIVE COMPONENT REQUIREMENTS . 34 APPLICATIONS 34 Superheterodyne Receiver 34 Synchronization of Multiple AD9874s . 36 Split Path Rx Architecture 37 Hung Mixer Mode 38 LAYOUT EXAMPLE EVALUATION BOARD AND SOFTWARE . 38 OUTLINE DIMENSIONS . 39 REVISION HISTORY 40 2 REV. A