Quad Pin Timing Formatter ADATE207 FEATURES FUNCTIONAL BLOCK DIAGRAM 4-channel timing formatter ADATE207 256 waveforms per channel PATTERN 4 independent event edges per waveform TIME SET QUAD EDGE DCL MEMORY GENERATOR FORMAT INTERFACE STIL IEEE 1450-1999-compatible events COMPARE LOGIC FAIL 4-period range for each edge FAIL DETECTION 39.06 ps timing resolution 2.5 ns minimum edge refire rate All drive formats supported PATTERN TIME SET QUAD EDGE DCL MEMORY GENERATOR FORMAT INTERFACE 100 MHz base vector rate COMPARE LOGIC 2 and 4 high speed modes FAIL FAIL DETECTION 2 pin multiplexing 1 ns minimum pulse width 32-bit fail counter per channel PATTERN TIME SET QUAD EDGE DCL 4-bit pin capture per channel MEMORY GENERATOR FORMAT INTERFACE COMPARE Air cooled, low power CMOS design LOGIC FAIL FAIL DETECTION 6 W at 100 MHz base rate 2.5 V power supply Differential DCL interface control PATTERN TIME SET QUAD EDGE TMU multiplexer DCL MEMORY GENERATOR FORMAT INTERFACE COMPARE LOGIC FAIL FAIL DETECTION APPLICATIONS Automatic test equipment (ATE) Figure 1. High speed digital instrumentation Pulse generation generators use a reference master clock of 100 MHz and provide programmable delays based upon counts of the clock and a GENERAL DESCRIPTION compensated CMOS analog timing vernier. The programmable The ADATE207 is a timing generator and formatter for auto- delay generators can be additionally delayed by a global 8-bit matic test equipment (ATE) equipment. The ADATE207 provides input value that is shared across all edges. four independent channels with a 100 MHz base vector rate of timing and formatting for ATE digital pins. It interfaces between The format and compare logic support 2 pin multiplexing to the pattern memory,and the driver, comparator, and load (DCL) allow the trading of pin count for speed. chips for complete digital pins. The ADATE207 accepts up to Each channel provides a 4-bit DUT output capture supporting eight bits of pattern data per pin and can produce formatted mixed signal receive memory applications. The fail detection outputs and perform comparisons of DUT expected responses. logic includes a 32-bit fail accumulation register per channel. Each channel of the ADATE207 provides 256 selectable wave- An external TMU is supported with three 8-to-1 multiplexers. forms, wherein each waveform consists of up to four possible This allows the dual comparator outputs of any pin to be events. Each event consists of a programmable timing edge and a multiplexed to any of the three outputs: arm, start, or stop STIL-compatible (IEEE Standard 1450-1999) set. signals. Each timing edge generator can produce an edge with a span of four periods with a 39.06 ps edge placement resolution. The delay Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 05557-001ADATE207 TABLE OF CONTENTS Features .............................................................................................. 1 Drive and Compare Logic......................................................... 13 Applications....................................................................................... 1 Pipeline Considerations............................................................. 14 Functional Block Diagram .............................................................. 1 DUT Capture .............................................................................. 15 General Description ......................................................................... 1 TMU Multiplexer ....................................................................... 15 Specifications..................................................................................... 3 Low Jitter Clock Driver ............................................................. 15 DC Specifications ......................................................................... 3 Clock Generator Mode.............................................................. 15 AC Specifications.......................................................................... 4 Device Reset................................................................................ 15 Timing Diagrams.......................................................................... 5 Temperature Diode .................................................................... 17 Absolute Maximum Ratings............................................................ 6 High Speed Differential DCL Interface................................... 17 Thermal Resistance ...................................................................... 6 Control and Status Register Interface .......................................... 18 Bypassing Scheme ........................................................................ 6 Read/Write Function ................................................................. 18 ESD Caution.................................................................................. 6 Control and Status Registers......................................................... 21 Pin Configurations and Function Descriptions ........................... 7 Channel Specific and Common Registers .............................. 22 Theory of Operation ...................................................................... 12 Chip-Specific (Common) Registers......................................... 30 Waveform Memory .................................................................... 12 Application Information ............................................................... 34 Event Generators ........................................................................ 12 Time Measurement Support ..................................................... 34 Delay Generation........................................................................ 12 Outline Dimensions....................................................................... 35 Vernier Resolution ..................................................................... 12 Ordering Guide .......................................................................... 35 REVISION HISTORY 5/07Revision 0: Initial Version Rev. 0 Page 2 of 36