ADF7025BCPZ Analog Devices

High Performance ISM Band Transceiver IC Data Sheet ADF7025 FEATURES On-chip VCO and Fractional-N PLL On-chip, 7-bit ADC and temperature sensor Low power, zero-IF RF transceiver Digital RSSI Frequency bands Integrated TRx switch 431 MHz to 464 MHz Leakage current < 1 A in power-down mode 862 MHz to 870 MHz 902 MHz to 928 MHz APPLICATIONS Data rates supported 9.6 kbps to 384 kbps, FSK Wireless audio/video 2.3 V to 3.6 V power supply Remote control/security systems Programmable output power Wireless metering 16 dBm to +13 dBm in 63 steps Keyless entry Receiver sensitivity Home automation 104.2 dBm at 38.4 kbps, FSK 100 dBm at 172.8 kbps, FSK 95.8 dBm at 384 kbps, FSK Low power consumption 19 mA in receive mode 28 mA in transmit mode (10 dBm output) FUNCTIONAL BLOCK DIAGRAM RSET CREG(1:4) ADCIN MUXOUT TEMP R BIAS LDO(1:4) LNA TEST MUX OFFSET SENSOR CORRECTION LNA FSK DATA RFIN MUX 7-BIT ADC DEMODULATOR SYNCHRONIZER LP FILTER RSSI RFINB GAIN OFFSET CE CORRECTION AGC DATA CLK CONTROL Tx/Rx DATA I/O CONTROL FSK MOD - CONTROL MODULATOR INT/LOCK DIVIDERS/ RFOUT DIV P N/N+1 MUXING SLE SDATA SERIAL PORT SREAD VCO SCLK CP PFD CLK DIV R RING OSC DIV VCOIN CPOUT CLKOUT OSC1 OSC2 Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20062016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 05542-001ADF7025 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Automatic Sync Word Recognition ......................................... 22 Applications ....................................................................................... 1 Applications Section....................................................................... 23 Functional Block Diagram .............................................................. 1 LNA/PA Matching ...................................................................... 23 Revision History ............................................................................... 2 Transmit Protocol and Coding Considerations ..................... 24 General Description ......................................................................... 3 Device Programming after Initial Power-Up ............................. 24 Specifications ..................................................................................... 4 Interfacing to Microcontroller/DSP ........................................ 24 Timing Characteristics ..................................................................... 7 Serial Interface ................................................................................ 27 Timing Diagrams .......................................................................... 7 Readback Format ........................................................................ 27 Absolute Maximum Ratings ............................................................ 9 Registers ........................................................................................... 28 ESD Caution .................................................................................. 9 Register 0N Register ............................................................... 28 Pin Configuration and Function Descriptions ........................... 10 Register 1Oscillator/Filter Register ...................................... 29 Typical Performance Characteristics ........................................... 12 Register 2Transmit Modulation Register ............................ 30 Frequency Synthesizer ................................................................... 15 Register 3Receiver Clock Register ....................................... 31 Reference Input Section ............................................................. 15 Register 4Demodulator Setup Register ............................... 32 Choosing Channels for Best System Performance ................. 17 Register 5Sync Byte Register ................................................. 33 Transmitter ...................................................................................... 18 Register 6Correlator/Demodulator Register ...................... 34 RF Output Stage .......................................................................... 18 Register 7Readback Setup Register ...................................... 35 Modulation Scheme ................................................................... 18 Register 8Power-Down Test Register .................................. 36 Receiver ............................................................................................ 19 Register 9AGC Register ......................................................... 37 RF Front End ............................................................................... 19 Register 10AGC 2 Register .................................................... 38 RSSI/AGC .................................................................................... 20 Register 12Test Register ......................................................... 39 FSK Demodulators on the ADF7025 ....................................... 20 Register 13Offset Removal and Signal Gain Register ....... 40 FSK Correlator/Demodulator ................................................... 20 Outline Dimensions ....................................................................... 41 Linear FSK Demodulator .......................................................... 22 Ordering Guide .......................................................................... 41 REVISION HISTORY 9/2016Rev. B to Rev. C 2/2006Rev. 0 to Rev. A Changes to General Description Section ...................................... 3 Replaced Figure 40 ................................................................ Page 29 Changes to Interfacing to Microcontroller/DSP Section and Figure 34 ........................................................................................... 24 1/2006Revision 0: Initial Version 8/2012Rev. A to Rev. B Changed CP-48-3 Package to CP-48-5 (Throughout) ................. 1 Added EPAD Notation to Figure 6 ............................................... 10 Updated Outline Dimensions ....................................................... 41 Changes to Ordering Guide .......................................................... 41 Rev. C Page 2 of 41