Data Sheet ADIN1100 Robust, Industrial, Low Power 10BASE-T1L PHY FEATURES FUNCTIONAL BLOCK DIAGRAM 10BASE-T1L IEEE Standard 802.3cg-2019 compliant Supports 1.0 V p-p and 2.4 V p-p transmit levels Supports intrinsic safety applications Cable reach <1700 meters with 1.0 V p-p <1700 meters with 2.4 V p-p Low power consumption Single supply 1 V p-p: 45 mW typical Dual supply 1 V p-p: 39 mW typical Diagnostics Frame generator and checker Multiple loopback modes IEEE test mode support Figure 1. Link and cable diagnostics MII, RMII, and RGMII MAC interfaces GENERAL DESCRIPTION MDIO management interface The ADIN1100 is a low power, single port, 10BASE-T1L transceiver Unmanaged configuration using pin strapping designed for industrial Ethernet applications and is compliant with 25 MHz crystal or external clock input (50 MHz for RMII) the IEEE 802.3cg-2019 Ethernet standard for long reach 10 Single or dual supply with 1.8 V or 3.3 V operation Mbps single pair Ethernet (SPE). The ADIN1100 integrates an Ethernet PHY core with all the associated analog circuitry, input and 3.3 V, 2.5 V, or 1.8 V MAC interface VDDIO supply output clock buffering, the management interface control register Integrated power supply monitoring and POR and subsystem registers, as well as the MAC interface and control EMC test standards logic to manage the reset, clock control, and pin configuration. IEC 61000-4-4 EFT (4 kV) The ADIN1100 supports cable reach of up to 1700 meters with IEC 61000-4-2 ESD (4 kV contact discharge) autonegotiation enabled and has ultra low power consumption of 39 IEC 61000-4-2 ESD (8 kV air discharge) mW. IEC 61000-4-5 surge (4 kV) The PHY core supports the 1.0 V p-p operating mode and the 2.4 V IEC 61000-4-6 conducted immunity (10 V/m) p-p operating mode defined in the IEEE 802.3cg standard and can IEC 61000-4-3 radiated immunity (Class A) operate from a single power supply rail of 1.8 V or 3.3 V, with the EN 55032 radiated emissions (Class B) lower voltage option supporting the 1.0 V p-p transmit voltage level. Small package: 40-lead, 6 mm 6 mm LFCSP The ADIN1100 has an integrated voltage supply monitoring circuit Temperature range and power-on reset (POR) circuitry to improve system level robust- Industrial: 40C to +85C ness. Extended: 40C to +105C The MDIO interface is a 2-wire serial interface for communication APPLICATIONS between a host processor or MAC and the ADIN1100, thereby allowing access to control and status information in the PHY core Process control management registers. This interface is compatible with both the Factory automation IEEE 802.3 Standard Clause 22 and Clause 45 management frame Building automation structures. Field instruments and switches Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliableas i. However, no responsibility is assumed by Analog DOCUMENT FEEDBACK Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and TECHNICAL SUPPORT registered trademarks are the property of their respective owners.Data Sheet ADIN1100 TABLE OF CONTENTS Features................................................................ 1 MII Control Register......................................... 39 Applications........................................................... 1 MII Status Register...........................................39 Functional Block Diagram......................................1 PHY Identifier 1 Register..................................40 General Description...............................................1 PHY Identifier 2 Register..................................40 Specifications........................................................ 5 MMD Access Control Register......................... 41 Timing Characteristics........................................... 8 MMD Access Register......................................41 Power-Up Timing................................................8 Ethernet Clause 45 Register Details................... 42 Management Interface Timing ...........................8 PMA/PMD Control 1 Register...........................44 Absolute Maximum Ratings...................................9 PMA/PMD Status 1 Register............................45 Thermal Resistance........................................... 9 PMA/PMD MMD Devices in Package 1 Electrostatic Discharge (ESD) Ratings...............9 Register..........................................................45 ESD Caution.......................................................9 PMA/PMD MMD Devices in Package 2 Pin Configuration and Function Descriptions...... 10 Register..........................................................45 Typical Performance Characteristics...................13 PMA/PMD Control 2 Register...........................45 Theory of Operation.............................................14 PMA/PMD Status 2 Register............................47 Power Supply Domains....................................14 PMA/PMD Transmit Disable Register.............. 47 MAC Interface.................................................. 14 PMA/PMD Extended Abilities Register.............47 Transmit Amplitude Configuration.................... 15 BASE-T1 PMA/PMD Extended Ability Master/Slave Configuration..............................15 Register..........................................................48 Autonegotiation................................................ 16 BASE-T1 PMA/PMD Control Register..............48 Management Interface..................................... 19 10BASE-T1L PMA Control Register.................48 Reset Operations............................................. 20 10BASE-T1L PMA Status Register..................49 Status LEDs..................................................... 20 10BASE-T1L Test Mode Control Register........49 Link Status Pin................................................. 22 10BASE-T1L PMA Link Status Register.......... 50 Power-Down Modes.........................................22 MSE Value Register......................................... 50 Hardware Configuration Pins...............................23 PCS Control 1 Register....................................50 Overview.......................................................... 23 PCS Status 1 Register..................................... 50 Unmanaged Applications................................. 23 PCS MMD Devices in Package 1 Register...... 51 Managed Applications......................................23 PCS MMD Devices in Package 2 Register...... 51 Hardware Configuration Pin Functions.............23 PCS Status 2 Register..................................... 51 Bringing Up 10BASE-T1L Links.......................... 26 10BASE-T1L PCS Control Register.................51 Unmanaged PHY Operation.............................26 10BASE-T1L PCS Status Register.................. 51 Managed PHY Operation................................. 26 Autonegotiation MMD Devices in Package 1 On-Chip Diagnostics............................................29 Register..........................................................52 Loopback Modes..............................................29 Autonegotiation MMD Devices in Package 2 Frame Generator and Checker........................ 30 Register..........................................................52 Frame Generator and Checker Link Test......... 30 BASE-T1 Autonegotiation Control Register..... 52 Test Modes.......................................................32 BASE-T1 Autonegotiation Status Register.......52 Applications Information...................................... 33 BASE-T1 Autonegotiation Advertisement System Level Power Management...................33 Register, Bits 15:0 ......................................... 53 LED Circuit Examples...................................... 33 BASE-T1 Autonegotiation Advertisement Component Recommendations........................34 Register, Bits 31:16 ....................................... 53 Electromagnetic Compatibility (EMC) and BASE-T1 Autonegotiation Advertisement Electromagnetic Immunity (EMI) ................... 35 Register, Bits 47:32 ....................................... 54 Register Summary...............................................36 BASE-T1 Autonegotiation Link Partner Base Clause 22......................................................... 36 Page Ability Register, Bits 15:0 ..................... 54 Clause 45......................................................... 37 BASE-T1 Autonegotiation Link Partner Base Recommended Register Operation..................38 Page Ability Register, Bits 31:16 ................... 55 Ethernet Clause 22 Register Details................... 39 analog.com Rev. 0 2 of 78