Robust, Industrial, Low Latency and Low Power 10 Mbps,100 Mbps, and 1 Gbps Ethernet PHY Data Sheet ADIN1300 FEATURES GENERAL DESCRIPTION 10BASE-Te/100BASE-TX/1000BASE-T IEEE 802.3 compliant The ADIN1300 is a low power, single port, Gigabit Ethernet MII, RMII, and RGMII MAC interfaces transceiver with low latency and power consumption specifications 1000BASE-T RGMII latency transmit < 68 ns, receive < 226 ns primarily designed for industrial Ethernet applications. 100BASE-TX MII latency transmit< 52 ns, receive < 248 ns This design integrates an energy efficient Ethernet (EEE) physical EMC test standards layer device (PHY) core with all associated common analog IEC 61000-4-5 surge (4 kV) circuitry, input and output clock buffering, management IEC 61000-4-4 electrical fast transient (EFT) (4 kV) interface and subsystem registers, and MAC interface and IEC 61000-4-2 ESD (6 kV contact discharge) control logic to manage the reset and clock control and pin IEC 61000-4-6 conducted immunity (10 V) configuration. EN55032 radiated emissions (Class A) The ADIN1300 is available in a 6 mm 6 mm, 40-lead lead EN55032 conducted emissions (Class A) frame chip scale package (LFCSP). The device operates with a Unmanaged configuration using multilevel pin strapping minimum of 2 power supplies, 0.9 V and 3.3 V, assuming the EEE in accordance with IEEE 802.3az use of a 3.3 V MAC interface supply. For maximum flexibility in Start of packet detection for IEEE 1588 time stamp support system level design, a separate VDDIO supply enables the Enhanced link detection management data input/output (MDIO) and MAC interface Configurable LED supply voltages to be configured independently of the other Crystal oscillator frequency/25 MHz clock input frequency circuitry on the ADIN1300, allowing operation at 1.8 V, 2.5 V, (50 MHz for RMII) or 3.3 V. At power-up, the ADIN1300 is held in hardware reset 25 MHz/125 MHz synchronous clock output until each of the supplies has crossed its minimum rising threshold Small package and wide temperature range value. Brown-out protection is provided by monitoring the 40-lead, 6 mm 6 mm LFCSP supplies to detect if one or more supply drops below a minimum Specified for 40C to +105C ambient operation falling threshold (see Table 17), and holding the device in Low power consumption hardware reset until the power supplies return and satisfy the 330 mW for 1000BASE-T power-on reset (POR) circuit. 140 mW for 100BASE-TX 3.3 V/2.5 V/1.8 V MAC interface VDDIO supply The MII management interface (also referred to as MDIO Integrated power supply monitoring and POR interface) provides a 2-wire serial interface between a host processor or MAC (also known as management station (STA)) APPLICATIONS and the ADIN1300, allowing access to control and status Industrial automation information in the PHY core management registers. The Process control interface is compatible with both the IEEE 802.3 Standard Factory automation Clause 22 and Clause 45 management frame structures. Robotics/motion control The ADIN1300 can support cable lengths up to 150 meters at Time sensitive networking (TSN) Gigabit speeds and 180 meters when operating at 100 Mbps or Building automation 10 Mbps. Test and measurement Industrial internet of things (IoT) Note that throughout this data sheet, multifunction pins, such as XTAL I/CLK IN/REF CLK, are referred to either by the entire pin name or by a single function of the pin, for example, XTAL I/CLK IN, when only that function is relevant. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. ADIN1300 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 On-Chip Diagnostics ..................................................................... 30 Applications ....................................................................................... 1 Loopback Modes ........................................................................ 30 General Description ......................................................................... 1 Frame Generator and Checker ................................................. 31 Revision History ............................................................................... 2 Cable Diagnostics ....................................................................... 32 Functional Block Diagram .............................................................. 3 Enhanced Link Detection ......................................................... 32 Specif icat ions ..................................................................................... 4 Start of Packet Indication .......................................................... 32 Timing Characteristics ................................................................ 6 Typical Power Consumption ......................................................... 34 Absolute Maximum Ratings .......................................................... 10 Applications Information .............................................................. 36 Thermal Resistance .................................................................... 10 System Overview ........................................................................ 36 ESD Caution ................................................................................ 10 Component Recommendations ............................................... 37 Pin Configuration and Function Descriptions ........................... 11 Power Requirements .................................................................. 37 Typical Performance Characteristics ........................................... 14 Supply Decoupling ..................................................................... 38 Theory of Operation ...................................................................... 16 Register Summary .......................................................................... 39 O ver vie w ...................................................................................... 16 PHY Core Register Summary ................................................... 39 Analog Front End (AFE) ........................................................... 16 PHY Core Register Details ........................................................ 41 MAC Interface ............................................................................ 17 Subsystem Register Summary .................................................. 72 Autonegotiation .......................................................................... 18 Subsystem Register Details ....................................................... 72 Autonegotiation Disabled .......................................................... 18 PCB Layout Recommendations .................................................... 78 Management Interface ............................................................... 18 PHY Package Layout .................................................................. 78 MDI Interface.............................................................................. 20 Component Placement .............................................................. 78 Reset Operation .......................................................................... 20 MDI, Differential Pair Routing ................................................ 78 Power-Down Modes .................................................................. 22 MAC Interface Pins .................................................................... 78 Status LED ................................................................................... 23 Power and Ground Planes ......................................................... 78 PHY Output Clocks ................................................................... 24 Outline Dimensions ....................................................................... 79 Power Supply Domains .............................................................. 24 Ordering Guide .......................................................................... 79 Hardware Configuration Pins ....................................................... 25 Hardware Configuration Pin Functions .................................. 25 REVISION HISTORY 10/2019Revision 0: Initial Version Rev. 0 Page 2 of 79