CPRI and 10G Ethernet Data Recovery IC with Amp/EQ from 614.4 Mbps to 10.3125 Gbps Data Sheet ADN2905 FEATURES GENERAL DESCRIPTION Serial CPRI data rates The ADN2905 provides the receiver functions of quantization and 614.4 Mbps, 1.2288 Gbps, 2.4576 Gbps, 3.072 Gbps, multirate data recovery at 614.4 Mbps, 1.2288 Gbps, 1.25 Gbps, 4.9152 Gbps, 6.144 Gbps, and 9.8304 Gbps 2.4576 Gbps, 3.072 Gbps, 4.9152 Gbps, 6.144 Gbps, 9.8304 Gbps, Ethernet data rates: 1.25 Gbps and 10.3125 Gbps and 10.3125 Gbps, used in Common Public Radio Interface No reference clock required (CPRI) and gigabit Ethernet applications. The ADN2905 Jitter performance superior to the SFF-8431 jitter specifications automatically locks to all the specified CPRI and Ethernet data Optional equalizer or 0 dB EQ input mode rates without the need for an external reference clock or Quantizer sensitivity: 200 mV p-p typical (equalizer mode) programming. The ADN2905 jitter performance exceeds the Sample phase adjust (5.65 Gbps or greater) jitter requirement specified by SFF-8431. Output polarity invert The ADN2905 provides manual sample phase adjustment. 2 I C to access optional features Additionally, the user can select an equalizer or a 0 dB EQ as the Loss of lock (LOL) indicator input. The equalizer is either adaptive or can be manually set. PRBS generator/detector The ADN2905 also supports pseudorandom binary sequence Application aware power (PRBS) generation, bit error detection, and input data rate 349.5 mW at 9.8304 Gbps, 0 dB EQ input mode readback features. 287.7 mW at 6.144 Gbps, 0 dB EQ input mode 249.3 mW at 3.072 Gbps, 0 dB EQ input mode The ADN2905 is available in a compact 4 mm 4 mm, 24-lead Power supply: 1.2 V, flexible 1.8 V to 3.3 V, and 3.3 V chip scale package (LFCSP). All ADN2905 specifications are 4 mm 4 mm, 24-lead LFCSP defined over the ambient temperature range of 40C to +85C, unless otherwise noted. APPLICATIONS SFF-8431-compatible Ethernet: 10GE, 1GE, and CPRI: OS/L.6 up to OS/L.96 FUNCTIONAL BLOCK DIAGRAM REFCLKP/ REFCLKN DATOUTP/ SCK SDA LOL (OPTIONAL) DATOUTN ADN2905 DATA RATE 2 2 I C REGISTERS I C ADDR FREQUENCY CML ACQUISITION AND LOCK DETECTOR CLK DDR SAMPLE FIFO PHASE N 2 ADJUST DOWNSAMPLER DCO AND LOOP FILTER DATA PIN 2 0dB EQ RXD INPUT NIN SAMPLER RXCK EQ 50 50 2 CLOCK I C PHASE 2 I C SHIFTER V V CM CC FLOAT Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20142016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com TXD 12624-001ADN2905 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 15 Applications ....................................................................................... 1 Functional Description .................................................................. 17 General Description ......................................................................... 1 Frequency Acquisition ............................................................... 17 Functional Block Diagram .............................................................. 1 Edge Select ................................................................................... 17 Revision History ............................................................................... 2 Passive Equalizer ........................................................................ 18 Specifications ..................................................................................... 3 0 dB EQ ........................................................................................ 18 Jitter Specifications ....................................................................... 4 Lock Detector Operation .......................................................... 18 Output and Timing Specifications ............................................. 5 Harmonic Detector .................................................................... 19 Timing Diagrams .......................................................................... 6 Output Disable and Squelch ..................................................... 19 2 Absolute Maximum Ratings ............................................................ 7 I C Interface ................................................................................ 20 Thermal Characteristics .............................................................. 7 Reference Clock (Optional) ...................................................... 20 2 ESD Caution .................................................................................. 7 Additional Features Available via the I C Interface ............... 22 Pin Configuration and Function Descriptions ............................. 8 Input Configurations ................................................................. 24 Typical Performance Characteristics ............................................. 9 DC-Coupled Application .......................................................... 26 2 I C Interface Timing and Internal Register Descriptions ......... 10 Outline Dimensions ....................................................................... 27 Register Map ............................................................................... 11 Ordering Guide .......................................................................... 27 REVISION HISTORY 1/16Rev 0. to Rev. A Changes to Figure 5 .......................................................................... 8 Updated Outline Dimensions ....................................................... 27 Changes to Ordering Guide .......................................................... 27 12/14Revision 0: Initial Version Rev. A Page 2 of 27