Continuous Rate 8.5 Gbps to 11.3 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ Data Sheet ADN2917 FEATURES GENERAL DESCRIPTION Serial data input: 8.5 Gbps to 11.3 Gbps The ADN2917 provides the receiver functions of quantization, No reference clock required signal level detect, and clock and data recovery for continuous data Exceeds SONET/SDH requirements for jitter rates from 8.5 Gbps to 11.3 Gbps. The ADN2917 automatically transfer/generation/tolerance locks to all data rates without the need for an external reference Quantizer sensitivity: 9.2 mV p-p typical clock or programming. ADN2917 jitter performance exceeds all (limiting amplifier mode) jitter specifications required by SONET/SDH, including jitter Optional limiting amplifier and equalizer inputs transfer, jitter generation, and jitter tolerance. Programmable jitter transfer bandwidth to support G.8251 OTN The ADN2917 provides manual or automatic slice adjust and Programmable slice level manual sample phase adjusts. Additionally, the user can select a Sample phase adjust limiting amplifier or equalizer at the input. The equalizer is Output polarity invert either adaptive or can be manually set. 2 Programmable LOS threshold via I C 2 The receiver front-end loss of signal (LOS) detector circuit I C to access optional features indicates when the input signal level has fallen below a user- LOS alarm (limiting amplifier mode only) programmable threshold. The LOS detect circuit has hysteresis LOL indicator to prevent chatter at the LOS output. In addition, the input PRBS generator/detector 2 signal strength can be read through the I C registers. Application-aware power 352 mW at 8.5 Gbps, equalizer mode, no clock output The ADN2917 also supports pseudorandom binary sequence 430 mW at 11.3 Gbps, equalizer mode, no clock output (PRBS) generation, bit error detection, and input data rate Power supplies: 1.2 V, flexible 1.8 V to 3.3 V, and 3.3 V readback features. 4 mm 4 mm 24-lead LFCSP The ADN2917 is available in a compact 4 mm 4 mm, 24-lead APPLICATIONS frame chip scale package (LFCSP). All ADN2917 specifications are defined over the ambient temperature range of 40C to +85C, SONET/SDH OC-192, 10GFC, and 10GE and all associated FECs unless otherwise noted. XFP, line cards, clocks, routers, repeaters, instruments Any rate regenerators/repeaters FUNCTIONAL BLOCK DIAGRAM REFCLKP/ REFCLKN DATOUTP/ CLKOUTP/ SCK SDA LOL (OPTIONAL) DATOUTN CLKOUTN 2 2 DATA RATE I C ADDR I C REGISTERS FREQUENCY CML CML ACQUISITION AND LOCK DETECTOR CLK DDR ADN2917 SAMPLE LOS FIFO PHASE LOS DETECT N 2 ADJUST DOWNSAMPLER DCO LA AND LOOP DATA FILTER PIN 2 RXD INPUT BYPASS NIN SAMPLER RXCK EQ 50 50 CLOCK 2 2 PHASE I C I C SHIFTER V V CM CC FLOAT Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20142017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. SLICE ADJUST LOS THRESH TXD 11778-001ADN2917 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Functional Description .................................................................. 20 Applications ....................................................................................... 1 Frequency Acquisition ............................................................... 20 General Description ......................................................................... 1 Limiting Amplifier ..................................................................... 20 Functional Block Diagram .............................................................. 1 Slice Adjust .................................................................................. 20 Revision History ............................................................................... 2 Edge Select ................................................................................... 20 Specif icat ions ..................................................................................... 3 Loss of Signal Detector .............................................................. 22 Jitter Specifications ....................................................................... 4 Passive Equalizer ........................................................................ 22 Output and Timing Specifications ............................................. 5 0 dB EQ ........................................................................................ 23 Timing Diagrams .......................................................................... 7 Lock Detector Operation .......................................................... 23 Absolute Maximum Ratings ............................................................ 8 Output Disable and Squelch ..................................................... 24 2 Thermal Characteristics .............................................................. 8 I C Interface ................................................................................ 24 ESD Caution .................................................................................. 8 Reference Clock (Optional) ...................................................... 24 2 Pin Configuration and Function Descriptions ............................. 9 Additional Features Available via the I C Interface ............... 26 Typical Performance Characteristics ........................................... 10 Input Configurations ................................................................. 28 2 I C Interface Timing and Internal Register Descriptions ......... 12 DC-Coupled Application .......................................................... 31 Register Map ............................................................................... 13 Outline Dimensions ....................................................................... 32 Theory of Operation ...................................................................... 18 Ordering Guide .......................................................................... 32 REVISION HISTORY 8/2017Rev. B to Rev. C 2/2016Rev. 0 to Rev. A Changed CP-24-8 to CP-24-7 ...................................... Throughout Changes to Figure 5 ........................................................................... 9 Changes to DATA SWING 3:0 Bit Description and Changes to Table 7 .......................................................................... 13 ClOCK SWING 3:0 Bit Description, Table 19 ........................ 17 Updated Outline Dimensions ....................................................... 32 Updated Outline Dimensions ....................................................... 32 Changes to Ordering Guide .......................................................... 32 Changes to Ordering Guide .......................................................... 32 5/2014Revision 0: Initial Version 7/2017Rev. A to Rev. B Change to Register CTRLC, Bit D0, Table 7 ............................... 13 Changes to Bit D0 Bit Name and Bit Description, Table 11 ..... 15 Updated Outlined Dimensions ..................................................... 32 Changes to Ordering Guide .......................................................... 32 Rev. C Page 2 of 32