4.25 Gbps, 16 16, Digital Crosspoint Switch Data Sheet ADN4604 FEATURES FUNCTIONAL BLOCK DIAGRAM DV V DC to 4.25 Gbps per port NRZ data rate CC CC Programmable receive equalization IP 15:0 OP 15:0 12 dB boost at 2 GHz RX TX 16 16 V , PRE- TTIE V , Compensates 40 inches of FR4 at 4.25 Gbps TTON SWITCH V TTIW EMPHASIS V TTOS MATRIX EQ Programmable transmit preemphasis/deemphasis IN 15:0 ON 15:0 Up to 12 dB boost at 4.25 Gbps Compensates 40 inches of FR4 at 4.25 Gbps Low power: 130 mW per channel at 3.3 V (outputs enabled) CONNECTION MAP 0 16 16, fully differential, nonblocking array Double rank connection programming with dual CONNECTION OUTPUT PER-PORT MAP 1 LEVEL OUTPUT connection maps HOOKUP LEVEL Low jitter, typically 20 ps TABLE SETTINGS RESET Flexible I/O supply range UPDATE SERIAL DC- or ac-coupled differential CML inputs I2C/SPI INTERFACE ADDR1/SDI CONTROL Programmable CML output levels ADDR0/CS LOGIC ADN4604 Per-lane input P/N pair inversion for routing ease SDA/SDO SCL/SCK 50 on-chip I/O termination Supports 8b/10b, scrambled or uncoded NRZ data V EE 2 Serial (I C slave or SPI) control interface Figure 1. 100-lead TQFP, Pb-free package APPLICATIONS Fiber optic network switching High speed serial backplane routing to OC-48 with FEC XAUI: 10GBASE-KX4 Gigabit Ethernet over backplane: 1000BASE-KX 1, 2, and 4 Fibre Channel InfiniBand Digital video (HDMI, DVI, DisplayPort, 3G-/HD-/SD-SDI) Data storage networks GENERAL DESCRIPTION The ADN4604 is a 16 16 asynchronous, protocol agnostic, The ADN4604 nonblocking switch core implements a 16 16 digital crosspoint switch, with 16 differential PECL-/CML- crossbar and supports independent channel switching through compatible inputs and 16 differential CML outputs. the serial control interface. The ADN4604 has low latency and very low channel-to-channel skew. The ADN4604 is optimized for nonreturn-to-zero (NRZ) sig- 2 naling with data rates of up to 4.25 Gbps per port. Each port An I C or SPI interface is used to control the device and pro- offers a fixed level of input equalization and programmable vide access to advanced features, such as additional levels of output swing and output preemphasis. preemphasis and output disable. The ADN4604 is packaged in a 100-lead TQFP package and operates from 40C to +85C. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20092013 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 07934-001ADN4604 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Switch Core ................................................................................. 17 Applications ....................................................................................... 1 Transmitters ................................................................................ 19 Functional Block Diagram .............................................................. 1 Termination ................................................................................. 23 2 General Description ......................................................................... 1 I C Serial Control Interface ........................................................... 24 Revision History ............................................................................... 2 Reset ............................................................................................. 24 2 Specifications ..................................................................................... 3 I C Data Write ............................................................................. 24 2 Electrical Specifications ............................................................... 3 I C Data Read .............................................................................. 25 2 I C Timing Specifications ............................................................ 4 SPI Serial Control Interface .......................................................... 26 SPI Timing Specifications ........................................................... 5 Register Map ................................................................................... 28 Absolute Maximum Ratings ............................................................ 6 Applications Information .............................................................. 32 ESD Caution .................................................................................. 6 Supply Sequencing ..................................................................... 34 Pin Configuration and Function Descriptions ............................. 7 Power Dissipation....................................................................... 34 Typical Performance Characteristics ........................................... 10 Output Compliance ................................................................... 34 Theory of Operation ...................................................................... 16 Printed Circuit Board (PCB) Layout Guidelines ................... 36 Introduction ................................................................................ 16 Outline Dimensions ....................................................................... 38 Receivers ...................................................................................... 16 Ordering Guide .......................................................................... 38 REVISION HISTORY 3/13Rev. 0 to Rev. A Changes to Switching Time Parameter and Operating Range Parameter, Table 1 .......................................................................................... 3 Changes to Logic Characteristics Parameters, Table 1 ................... 4 Changes to Receivers Section ...................................................................... 16 Changes to Switch Core Section ................................................................. 17 Changes to Transmitters Section and Figure 42 ...................................... 19 Changes to Basic Settings Section and Table 11 ....................................... 20 Change to Table 18 ....................................................................................... 29 10/09Revision 0: Initial Version Rev. A Page 2 of 40