4.25 Gbps 40 40 Digital Crosspoint Switch Data Sheet ADN4605 FEATURES FUNCTIONAL BLOCK DIAGRAM DV V CC CC DC to 4.25 Gbps per port NRZ data rate Adjustable receive equalization IP 39:0 Rx Tx OP 39:0 40 40 V , 3 dB, 6 dB, or 12 dB boost TTIA PRE- V , TTOA SWITCH V EMPHASIS TTIB V MATRIX TTOB EQ Compensates over 40 inches of FR4 at 4.25 Gbps IN 39:0 ON 39:0 Adjustable transmit preemphasis/deemphasis EQUALIZATION Programmable boost and output level SETTINGS Compensates over 40 inches of FR4 at 4.25 Gbps Low power CONNECTION MAP 1 PRE- OUTPUT 105 mW per channel at 2.5 V (400 mV p-p differential EMPHASIS LEVEL LEVEL CONNECTION SETTINGS SETTINGS output level swing) MAP 0 40 40, fully differential, nonblocking array RESET DATA 0 / Double rank connection programming with dual maps SER/PAR SDA/SDO 2 I C/SPI DATA 1 Low jitter, typically <25 ps PARALLEL/SERIAL CONTROL (UPDATE) (UPDATE) LOGIC INTERFACE Flexible 2.5 V to 3.3 V supply range CS DATA 7:2 SCL/SCK/ ADDR 7:0 WE DC- or ac-coupled differential PECL/CML inputs SDI/RE ADN4605 Differential CML outputs V EE Per-lane polarity inversion for routing ease Figure 1. 50 on-chip I/O termination with disable feature Supports 8b10b, scrambled or uncoded NRZ data Serial (IC slave or SPI) control interface Parallel control interface APPLICATIONS Digital video (HDMI, DVI, DisplayPort, 3G/HD/SD-SDI) Fiber optic network switching High speed serial backplane routing to OC-48 with FEC XAUI, 4x Fibre Channel, Infiniband, and GbE over backplane Data storage networks GENERAL DESCRIPTION The ADN4605 is a 40 40 asynchronous, protocol agnostic, The ADN4605 nonblocking switch core implements a 40 40 digital crosspoint switch, with 40 differential PECL/CML- crossbar and supports independent channel switching through compatible inputs and 40 differential programmable CML outputs. serial and parallel control interfaces. The ADN4605 has low latency and very low channel-to-channel skew. The ADN4605 is optimized for NRZ signaling with data rates of 2 up to 4.25 Gbps per port. Each port offers adjustable levels of An I C, SPI, or parallel interface is used to communicate with input equalization, programmable output swing, and output the device for control of connectivity and other features. preemphasis/deemphasis. The ADN4605 is assembled in a 35 mm 35 mm, 352 BGA package and operates over a temperature range of 40C to +85C. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 09796-001ADN4605 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Transmitters ................................................................................ 29 Functional Block Diagram .............................................................. 1 Ter minat ion ................................................................................. 32 2 Applications ....................................................................................... 1 I C Serial Control Interface ........................................................... 33 2 General Description ......................................................................... 1 I C Data Write ............................................................................. 33 2 Revision History ............................................................................... 2 I C Data Read .............................................................................. 34 Specif icat ions ..................................................................................... 3 SPI Serial Control Interface .......................................................... 35 Electrical Specifications ............................................................... 3 Parallel Control Interface .............................................................. 38 2 I C Timing Specifications ............................................................ 5 Address Inputs: ADDR 7:0 ...................................................... 38 SPI Timing Specifications ........................................................... 5 Data Inputs/Outputs: DATA 7:0 ............................................. 38 Parallel Mode Specifications ....................................................... 6 Write Operation.......................................................................... 38 Absolute Maximum Ratings ............................................................ 7 Read Operation........................................................................... 38 Thermal Resistance ...................................................................... 7 Register Map ................................................................................... 39 ESD Caution .................................................................................. 7 Applications Information .............................................................. 49 Pin Configuration and Function Descriptions ............................. 8 Supply Sequencing ..................................................................... 51 Typical Performance Characteristics ........................................... 18 Power Dissipation....................................................................... 51 Theory of Operation ...................................................................... 24 Output Compliance ................................................................... 51 Introduction ................................................................................ 24 TX/XPT HEADROOM ............................................................. 51 Receivers ...................................................................................... 25 PCB Layout Guidelines .............................................................. 54 Polarity Inversion ....................................................................... 26 Outline Dimensions ....................................................................... 55 Switch Core ................................................................................. 27 Ordering Guide .......................................................................... 55 Reset ............................................................................................. 28 REVISION HISTORY 7/2019Rev. A to Rev. B 11/2011Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 4 Changes to Printed Circuit Board (PCB) Layout Changes to Table 6 ............................................................................ 7 Guidelines ........................................................................................ 54 Added Thermal Resistance Section and Table 7 Removed Figure 55, Renumbered Sequentially ......................... 54 Renumbered Sequentially ................................................................ 7 6/2011Revision 0: Initial Version Updated Outline Dimensions ....................................................... 55 Change to Ordering Guide ............................................................ 55 Rev. B Page 2 of 56