11.3 Gbps, 12 12 Digital Crosspoint Switch Data Sheet ADN4612 FEATURES FUNCTIONAL BLOCK DIAGRAM DVCC VCC DC to 11.3 Gbps per port, NRZ data rate Multitime constant, programmable receive equalization Compensates 25 inches of FR408 at 10.3125 Gbps IP11 OP11 Tx Rx Compensates 15 inches of FR408 at 11.3 Gbps TO IP0 TO OP0 12 12 PRE- VTTIE, 6-tap programmable transmit feedforward equalization (FFE) VTTON, SWITCH EMPHASIS VTTIW VTTOS MATRIX Compensates 15 inches of FR408 at 10.3125 Gbps EQ ON11 IN11 TO ON0 TO IN0 Compensates 10 inches of FR408 at 11.3 Gbps Low power 150 mW per channel at 2.5 V (outputs enabled) XPT CONTROL Rx CONTROL Tx CONTROL CONNECTIVITY EQUALIZATION 6-TAP FFE 12 12, fully differential, nonblocking array MAP (A/B/C/D) SIGNAL DETECT OUTPUT LEVEL SELECT Double rank connection programming 2-pin selectable connection maps Per lane lost of signal (LOS) detection EEPROM MAP1, MAP0 Flexible output termination supply range (1.8 V to 3.3 V) DC- or ac-coupled differential CML inputs and outputs RESET SERIAL Programmable CML output levels UPDATE INTERFACE 2 SPI/I C Load from EEPROM for automatic power-on ready operation CONTROL LOGIC SCK/SCL Per lane input and output P/N pair inversion for routing ease SDO/SDA ADN4612 50 on-chip input/output termination 2 SDI/I C A1 Supports 64-bit/66-bit, scrambled or not coded NRZ data up 2 CS/I C A0 to 11.3 Gbps LOS IRQ 2 Serial (I C or SPI slave) control interface VEE 88-lead LFCSP, 12 mm 12 mm, Pb-free package Figure 1. 40C to +85C operating temperature range APPLICATIONS Fiber optic network switching 10 Gigabit Ethernet over backplane 10GBASE-KR 802.3ap XLAUI/CAUI (802.3ba) SONET OC-192/STM-64x 1, 2, 4, 8, and 10 Fibre Channel GENERAL DESCRIPTION The ADN4612 is a 12 12 asynchronous, protocol agnostic, digital The ADN4612 nonblocking switch core implements a 12 12 crosspoint switch with 12 differential PECL-/CML-compatible crossbar and supports independent channel switching through inputs and 12 differential CML outputs. the serial control interface. The ADN4612 has low latency and very low channel-to-channel skew. The ADN4612 is optimized for nonreturn-to-zero (NRZ) signaling with data rates of up to 11.3 Gbps per port. Each port provides The ADN4612 is packaged in an 88-lead LFCSP package and programmable input equalization, loss of signal (LOS) detection, operates from 40C to +85C. programmable output swing, and output preemphasis/deemphasis. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20132016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 11020-001ADN4612 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register Descriptions ..................................................................... 47 Applications ....................................................................................... 1 Software Reset Register ............................................................. 47 Functional Block Diagram .............................................................. 1 Tx Enable Control Registers ..................................................... 47 General Description ......................................................................... 1 Tx Reference Enable Register ................................................... 48 Revision History ............................................................................... 3 Squelch Control Register ........................................................... 48 Specifications ..................................................................................... 4 Rx and Tx Swap Sign Registers ................................................. 48 Input/Output Specifications ........................................................ 4 XPT Broadcast Lane Number Register ................................... 50 Power Supply and Thermal Specifications ................................ 5 Tx 0 Driver Control Registers .................................................. 50 Electrical SpecificationsControl Logic Pins .......................... 6 Tx 0 Driver Enable Registers .................................................... 52 2 I C Master and Slave Timing Specifications ............................. 6 Tx 0 Driver Resolution Registers ............................................. 53 SPI Timing Specifications ........................................................... 7 Tx 1 Driver Control Registers .................................................. 53 2 EEPROM Tx 1 Driver Enable Registers .................................................... 53 Master I C Timing Specifications ............................ 8 Tx 1 Driver Resolution Registers ............................................. 53 RESET Timing Specifications ..................................................... 9 Tx 2 Driver Control Registers .................................................. 54 Absolute Maximum Ratings .......................................................... 10 Tx 2 Driver Enable Registers .................................................... 54 Thermal Resistance .................................................................... 10 Tx 2 Driver Resolution Registers ............................................. 54 ESD Caution ................................................................................ 10 Tx 3 Driver Control Registers .................................................. 54 Pin Configuration and Function Descriptions ........................... 11 Tx 3 Driver Enable Registers .................................................... 54 Typical Performance Characteristics ........................................... 13 Tx 3 Driver Resolution Registers ............................................. 54 Standard Test ............................................................................... 17 Tx 4 Driver Control Registers .................................................. 54 Equalization Test ........................................................................ 18 Tx 4 Driver Enable Registers .................................................... 54 Preemphasis Test ........................................................................ 20 Tx 4 Driver Resolution Registers ............................................. 55 Test Circuits ..................................................................................... 22 Tx 5 Driver Control Registers .................................................. 55 Theory of Operation ...................................................................... 23 Tx 5 Driver Enable Registers .................................................... 55 Introduction ................................................................................ 23 Tx 5 Driver Resolution Registers ............................................. 55 Receivers ...................................................................................... 24 Tx 6 Driver Control Registers .................................................. 55 Switch Core ................................................................................. 26 Tx 6 Driver Enable Registers .................................................... 55 Transmitters ................................................................................ 27 Tx 6 Driver Resolution Registers ............................................. 55 Preemphasis/Deemphasis Support for Legacy Rates ............. 33 Tx 7 Driver Control Registers .................................................. 55 Load from Memory .................................................................... 34 2 Tx 7 Driver Enable Registers .................................................... 55 I C Serial Control Interface ........................................................... 37 2 Tx 7 Driver Resolution Registers ............................................. 56 I C Data Write ............................................................................. 37 2 Tx 8 Driver Control Registers .................................................. 56 I C Data Read .............................................................................. 38 Tx 8 Driver Enable Registers .................................................... 56 SPI Serial Control Interface ........................................................... 39 Tx 8 Driver Resolution Registers ............................................. 56 Write Operation .......................................................................... 39 Tx 9 Driver Control Registers .................................................. 56 Read Operation ........................................................................... 39 Tx 9 Driver Enable Registers .................................................... 56 Applications Information .............................................................. 40 Tx 9 Driver Resolution Registers ............................................. 56 Applications Circuit ................................................................... 41 Tx 10 Driver Control Registers ................................................ 56 Power Consumption .................................................................. 41 Tx 10 Driver Enable Registers .................................................. 56 Printed Circuit Board (PCB) Layout Guidelines ................... 42 Tx 10 Driver Resolution Registers ........................................... 57 Register Map .................................................................................... 44 Rev. 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