Integrated Dual RF Transmitter, Receiver, and Observation Receiver Data Sheet ADRV9009 In addition to automatic gain control (AGC), the ADRV9009 FEATURES also features flexible external gain control modes, allowing Dual transmitters significant flexibility in setting system level gain dynamically. Dual receivers Dual input shared observation receiver The received signals are digitized with a set of four high dynamic Maximum receiver bandwidth: 200 MHz range, continuous time - ADCs that provide inherent Maximum tunable transmitter synthesis bandwidth: antialiasing. The combination of the direct conversion 450 MHz architecture, which does not suffer from out of band image Maximum observation receiver bandwidth: 450 MHz mixing, and the lack of aliasing, relaxes the requirements of the Fully integrated fractional-N RF synthesizers RF filters when compared to traditional intermediate frequency Fully integrated clock synthesizer (IF) receivers. Multichip phase synchronization for RF LO and baseband The transmitters use an innovative direct conversion clocks modulator that achieves high modulation accuracy with JESD204B datapath interface exceptionally low noise. Tuning range (center frequency): 75 MHz to 6000 MHz The observation receiver path consists of a wide bandwidth, APPLICATIONS direct conversion receiver with state-of-the-art dynamic range. 3G, 4G, and 5G TDD macrocell base stations The fully integrated phase-locked loop (PLL) provides high TDD active antenna systems performance, low power, fractional-N RF frequency synthesis Massive multiple input, multiple output (MIMO) for the transmitter (Tx) and receiver (Rx) signal paths. An Phased array radar additional synthesizer generates the clocks needed for the Electronic warfare converters, digital circuits, and the serial interface. A multichip Military communications synchronization mechanism synchronizes the phase of the RF Portable test equipment local oscillator (LO) and baseband clocks between multiple ADRV9009 chips. Precautions are taken to provide the isolation GENERAL DESCRIPTION required in high performance base station applications. All The ADRV9009 is a highly integrated, radio frequency (RF), agile voltage controlled oscillators (VCOs) and loop filter transceiver offering dual transmitters and receivers, integrated components are integrated. synthesizers, and digital signal processing functions. The IC The high speed JESD204B interface supports up to 12.288 Gbps delivers a versatile combination of high performance and low lane rates, resulting in two lanes per transmitter and a single power consumption demanded by 3G, 4G, and 5G macro cell lane per receiver in the widest bandwidth mode. The interface time division duplex (TDD) base station applications. also supports interleaved mode for lower bandwidths, thus The receive path consists of two independent, wide bandwidth, reducing the total number of high speed data interface lanes to direct conversion receivers with state-of-the-art dynamic range. one. Both fixed and floating point data formats are supported. The device also supports a wide bandwidth, time shared The floating point format allows internal AGC to be invisible to observation path receiver (ORx) for use in TDD applications. the demodulator device. The complete receive subsystem includes automatic and The core of the ADRV9009 can be powered directly from 1.3 V manual attenuation control, dc offset correction, quadrature error regulators and 1.8 V regulators, and is controlled via a standard correction (QEC), and digital filtering, thus eliminating the need 4-wire serial port. Comprehensive power-down modes are for these functions in the digital baseband. Several auxiliary functions, such as analog-to-digital converters (ADCs), digital-to- included to minimize power consumption in normal use. The ADRV9009 is packaged in a 12 mm 12 mm, 196-ball chip analog converters (DACs), and general-purpose inputs/outputs scale ball grid array (CSP BGA). (GPIOs) for the power amplifier (PA), and RF front-end control are also integrated. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20182019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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ADRV9009 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 98 Applications ....................................................................................... 1 Transmitter .................................................................................. 98 General Description ......................................................................... 1 Receiver........................................................................................ 98 Revision History ............................................................................... 2 Observation Receiver ................................................................. 98 Functional Block Diagram .............................................................. 4 Clock Input .................................................................................. 98 Specif icat ions ..................................................................................... 5 Synthesizers ................................................................................. 98 Current and Power Consumption Specifications ................... 14 SPI ................................................................................................. 99 Timing Diagrams ........................................................................ 15 JTAG Boundary Scan ................................................................. 99 Absolute Maximum Ratings .......................................................... 16 Power Supply Sequence ............................................................. 99 Reflow Profile .............................................................................. 16 GPIO x Pins ............................................................................... 99 Thermal Management ............................................................... 16 Auxiliary Converters .................................................................. 99 Thermal Resistance .................................................................... 16 JESD204B Data Interface .......................................................... 99 ESD Caution ................................................................................ 16 Applications Information ............................................................ 101 Pin Configuration and Function Descriptions ........................... 17 PCB Layout and Power Supply Recommendations ............. 101 Typical Performance Characteristics ........................................... 23 PCB Material and Stackup Selection ..................................... 101 75 MHz to 525 MHz Band ........................................................ 23 Fanout and Trace Space Guidelines ....................................... 103 650 MHz to 3000 MHz Band .................................................... 44 Component Placement and Routing Guidelines ................. 104 3400 MHz to 4800 MHz Band .................................................. 63 RF and JESD204B Transmission Line Layout ...................... 110 5100 MHz to 5900 MHz Band .................................................. 80 Isolation Techniques Used on the ADRV9009-W/PCBZ ... 114 Transmitter Output Impedance ................................................ 95 RF Port Interface Information ................................................ 116 Observation Receiver Input Impedance .................................. 95 Outline Dimensions ..................................................................... 127 Receiver Input Impedance......................................................... 96 Ordering Guide ........................................................................ 127 Terminology .................................................................................... 97 REVISION HISTORY 5/2019Rev. A to Rev B. Changes to Terminology Section ................................................. 97 Replaced ADRV9009 Customer Card to Deleted Figure 432 ......................................................................... 98 ADRV9009-WPCBZ ..................................................... Throughout Changes to Theory of Operation Section and Clock Changes to Features Section............................................................ 1 Input Section ................................................................................... 98 Changes to Figure 1 .......................................................................... 4 Changed Serial Peripheral Interface Section to SPI Section and Changes to Specifications Section and Table 1 ............................. 5 AUX DAC x Section to Auxiliary DAC x Section ......................... 99 Change to Figure 2 ......................................................................... 15 Changes to Power Supply Sequence Section, GPIO x Pins Changes to Table 3 and Thermal Resistance Section ................. 16 Section, Auxiliary DAC x Section, and JESD204B Data Changes to 75 MHz to 525 MHz Band Section, Figures and Interface Section ............................................................................. 99 Captions ........................................................................................... 23 Changes to Table 7 Title, Figure 430, and Figure 431................... 100 Deleted Figure 83 to Figure 85 Renumbered Sequentially ...... 34 Changes to Overview Section, PCB Material and Stackup Added Figure 78, Figure 79, and Figure 80 Renumbered Selection Section, and Figure 432 Caption ............................... 101 Sequentially ..................................................................................... 35 Changes to Table 9 and Table 10 ................................................ 102 Added Figure 90 .............................................................................. 37 Changes to Fanout and Trace Space Guidelines Section ......... 103 Added Figure 125 to Figure 127 ................................................... 43 Changes to Signals with Highest Routing Priority Section and Changes to 650 MHz to 3000 MHz Band Section, Figures and Figure 434 ...................................................................................... 104 Captions ........................................................................................... 44 Change to Figure 435 Caption .................................................... 105 Changes to 3400 MHz to 4800 MHz Band Section, Figures and Changes to Signals with Second Routing Priority Section and Captions ........................................................................................... 63 Figure 436 ...................................................................................... 106 Changes to 5100 MHz to 5900 MHz Band Section, Figures and Changes to Figure 437 ................................................................. 107 Captions ........................................................................................... 80 Changes to Figure 438 ................................................................. 108 Rev. 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